s390x: Fix regalloc checker error (bytecodealliance#4973)

For ShiftRR and VecShiftRR, if shift_reg is zero_reg(), the instruction does not actually use any register value. Fixes bytecodealliance#4969
gurry · Sep 28, 2022 · 83bb6fd · 83bb6fd
1 parent cdecc85
commit 83bb6fd
Showing 1 changed file with 6 additions and 2 deletions.
diff --git a/cranelift/codegen/src/isa/s390x/inst/mod.rs b/cranelift/codegen/src/isa/s390x/inst/mod.rs
@@ -539,7 +539,9 @@ fn s390x_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut OperandC
         } => {
             collector.reg_def(rd);
             collector.reg_use(rn);
-            collector.reg_use(shift_reg);
+            if shift_reg != zero_reg() {
+                collector.reg_use(shift_reg);
+            }
         }
         &Inst::RxSBG { rd, rn, .. } => {
             collector.reg_mod(rd);
@@ -744,7 +746,9 @@ fn s390x_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut OperandC
         } => {
             collector.reg_def(rd);
             collector.reg_use(rn);
-            collector.reg_use(shift_reg);
+            if shift_reg != zero_reg() {
+                collector.reg_use(shift_reg);
+            }
         }
         &Inst::VecSelect { rd, rn, rm, ra, .. } => {
             collector.reg_def(rd);