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Push 2025 02 16 #910

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merged 14 commits into from
Feb 17, 2025
Merged

Push 2025 02 16 #910

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5cd7580
support non-zero PCICFG segment through 'MSR' driver
rdementi Feb 12, 2025
d118c41
convert some debug messages into DBG
rdementi Feb 12, 2025
9a81634
scan more PCICFG segments on GNR/Windows
rdementi Feb 12, 2025
6afb27e
convert errors to warnings
rdementi Feb 13, 2025
7e1c7f1
support non-zero PCI segment groupnr on *BSD
rdementi Feb 14, 2025
bd80503
avoid using PCM::getInstance in getMCFGRecords because of a deadlock
rdementi Feb 14, 2025
7f005db
pcm-power: support tpmi perf limit reason telemetry
rdementi Feb 14, 2025
5dd5610
add comments/docs
rdementi Feb 15, 2025
4ef3d03
rename extract_bits_ui into extract_bits_32
rdementi Feb 16, 2025
285417a
add extract_bits_64
rdementi Feb 16, 2025
b9695b5
debug: print version from PLR_HEADER
rdementi Feb 16, 2025
03a0134
debug: convert to DBG macro in cpucounters.h
rdementi Feb 16, 2025
82a5e43
debug: convert to DBG macro in utils.*
rdementi Feb 16, 2025
e8d9f7a
Merge tag '2025-02-16' into push-2025-02-16
rdementi Feb 17, 2025
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58 changes: 27 additions & 31 deletions src/cpucounters.cpp
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Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -253,13 +253,13 @@ void PCM::readCoreCounterConfig(const bool complainAboutMSR)
// get counter related info
PCM_CPUID_INFO cpuinfo;
pcm_cpuid(0xa, cpuinfo);
perfmon_version = extract_bits_ui(cpuinfo.array[0], 0, 7);
core_gen_counter_num_max = extract_bits_ui(cpuinfo.array[0], 8, 15);
core_gen_counter_width = extract_bits_ui(cpuinfo.array[0], 16, 23);
perfmon_version = extract_bits_32(cpuinfo.array[0], 0, 7);
core_gen_counter_num_max = extract_bits_32(cpuinfo.array[0], 8, 15);
core_gen_counter_width = extract_bits_32(cpuinfo.array[0], 16, 23);
if (perfmon_version > 1)
{
core_fixed_counter_num_max = extract_bits_ui(cpuinfo.array[3], 0, 4);
core_fixed_counter_width = extract_bits_ui(cpuinfo.array[3], 5, 12);
core_fixed_counter_num_max = extract_bits_32(cpuinfo.array[3], 0, 4);
core_fixed_counter_width = extract_bits_32(cpuinfo.array[3], 5, 12);
}
else if (1 == perfmon_version)
{
Expand Down Expand Up @@ -321,7 +321,7 @@ bool PCM::isFixedCounterSupported(unsigned c)
{
PCM_CPUID_INFO cpuinfo;
pcm_cpuid(0xa, cpuinfo);
return extract_bits_ui(cpuinfo.reg.ecx, c, c) || (extract_bits_ui(cpuinfo.reg.edx, 4, 0) > c);
return extract_bits_32(cpuinfo.reg.ecx, c, c) || (extract_bits_32(cpuinfo.reg.edx, 4, 0) > c);
}
return false;
}
Expand All @@ -340,7 +340,7 @@ bool PCM::isHWTMAL1Supported() const
supported = 0;
PCM_CPUID_INFO cpuinfo;
pcm_cpuid(1, cpuinfo);
if (extract_bits_ui(cpuinfo.reg.ecx, 15, 15) && MSR.size())
if (extract_bits_32(cpuinfo.reg.ecx, 15, 15) && MSR.size())
{
uint64 perf_cap;
if (MSR[0]->read(MSR_PERF_CAPABILITIES, &perf_cap) == sizeof(uint64))
Expand Down Expand Up @@ -1125,12 +1125,12 @@ bool PCM::discoverSystemTopology()
{
pcm_cpuid(0x1F, subleaf, cpuid_args);
domain d;
d.type = (TopologyEntry::DomainTypeID)extract_bits_ui(cpuid_args.reg.ecx, 8, 15);
d.type = (TopologyEntry::DomainTypeID)extract_bits_32(cpuid_args.reg.ecx, 8, 15);
if (d.type == TopologyEntry::DomainTypeID::InvalidDomainTypeID)
{
break;
}
d.nextLevelShift = extract_bits_ui(cpuid_args.reg.eax, 0, 4);
d.nextLevelShift = extract_bits_32(cpuid_args.reg.eax, 0, 4);
d.levelShift = topologyDomains.empty() ? 0 : topologyDomains.back().nextLevelShift;
d.width = d.nextLevelShift - d.levelShift;
topologyDomains.push_back(d);
Expand Down Expand Up @@ -1182,11 +1182,11 @@ bool PCM::discoverSystemTopology()
if (di != topologyDomainMap.end())
{
const auto & d = di->second;
return extract_bits_ui(apic_id, d.levelShift, d.nextLevelShift - 1);
return extract_bits_32(apic_id, d.levelShift, d.nextLevelShift - 1);
}
return 0U;
};
entry.tile_id = extract_bits_ui(getAPICID(0xb), l2CacheMaskShift, 31);
entry.tile_id = extract_bits_32(getAPICID(0xb), l2CacheMaskShift, 31);
const int apic_id = getAPICID(0x1F);
entry.thread_id = getID(apic_id, TopologyEntry::DomainTypeID::LogicalProcessorDomain);
entry.core_id = getID(apic_id, TopologyEntry::DomainTypeID::CoreDomain);
Expand All @@ -1210,7 +1210,7 @@ bool PCM::discoverSystemTopology()
};
domain d1 = getDomain( TopologyEntry::DomainTypeID::CoreDomain );
domain d2 = getDomain( TopologyEntry::DomainTypeID::SocketPackageDomain );
entry.socket_unique_core_id = extract_bits_ui( apic_id, d1.levelShift, d2.levelShift - 1 );
entry.socket_unique_core_id = extract_bits_32( apic_id, d1.levelShift, d2.levelShift - 1 );
}
else
{
Expand All @@ -1233,8 +1233,8 @@ bool PCM::discoverSystemTopology()
(void)core;
return false;
#endif
entry.native_cpu_model = extract_bits_ui(cpuid_args.reg.eax, 0, 23);
entry.core_type = (TopologyEntry::CoreType) extract_bits_ui(cpuid_args.reg.eax, 24, 31);
entry.native_cpu_model = extract_bits_32(cpuid_args.reg.eax, 0, 23);
entry.core_type = (TopologyEntry::CoreType) extract_bits_32(cpuid_args.reg.eax, 24, 31);
return true;
};

Expand Down Expand Up @@ -1654,7 +1654,7 @@ bool PCM::detectNominalFrequency()
{
PCM_CPUID_INFO cpuinfo;
pcm_cpuid(0x16, cpuinfo);
nominal_frequency = uint64(extract_bits_ui(cpuinfo.reg.eax, 0, 15)) * 1000000ULL;;
nominal_frequency = uint64(extract_bits_32(cpuinfo.reg.eax, 0, 15)) * 1000000ULL;;
}
if (!nominal_frequency)
{
Expand Down Expand Up @@ -2335,7 +2335,7 @@ void PCM::initUncorePMUsDirect()
addPMUsFromDiscoveryRef(uncorePMUs[s][0][PCU_PMU_ID], SPR_PCU_BOX_TYPE, 0xE);
if (uncorePMUs[s][0][PCU_PMU_ID].empty())
{
std::cerr << "ERROR: PCU PMU not found\n";
std::cerr << "WARNING: PCU PMU not found\n";
}
break;
}
Expand All @@ -2347,7 +2347,7 @@ void PCM::initUncorePMUsDirect()
addPMUsFromDiscoveryRef(uncorePMUs[s][0][MDF_PMU_ID], boxType);
if (uncorePMUs[s][0][MDF_PMU_ID].empty())
{
std::cerr << "ERROR: MDF PMU not found\n";
std::cerr << "WARNING: MDF PMU not found\n";
}
};
switch (cpu_family_model)
Expand Down Expand Up @@ -6224,7 +6224,7 @@ PCM::ErrorCode PCM::program(const RawPMUConfigs& curPMUConfigs_, const bool sile
const auto pcicfgOffset = extract_bits(membarBits, 0, 15);
uint32 memBarOffset = 0;
pciHandle.read32(pcicfgOffset, &memBarOffset);
return size_t(extract_bits_ui(memBarOffset, srcPos, srcPos + numBits - 1)) << destPos;
return size_t(extract_bits_32(memBarOffset, srcPos, srcPos + numBits - 1)) << destPos;
}
return 0;
};
Expand Down Expand Up @@ -6686,7 +6686,7 @@ void PCM::readPCICFGRegisters(SystemCounterState& systemState)
{
case 16:
h->read32(offset, &value32);
value = (uint64)extract_bits_ui(value32, 0, 15);
value = (uint64)extract_bits_32(value32, 0, 15);
break;
case 32:
h->read32(offset, &value32);
Expand Down Expand Up @@ -6756,7 +6756,7 @@ void PCM::readMMIORegisters(SystemCounterState& systemState)
{
case 16:
value32 = h->read32(offset);
value = (uint64)extract_bits_ui(value32, 0, 15);
value = (uint64)extract_bits_32(value32, 0, 15);
break;
case 32:
value32 = h->read32(offset);
Expand Down Expand Up @@ -9867,7 +9867,7 @@ uint64 ServerUncorePMUs::computeQPISpeed(const uint32 core_nr, const int cpufami
uint32 value = 0;
if (reg.read32(UPI_SPEED_REGISTER_OFFSET, &value) == sizeof(uint32))
{
const size_t speedMT = UPISpeedMap[extract_bits_ui(value, regBits.first, regBits.second)];
const size_t speedMT = UPISpeedMap[extract_bits_32(value, regBits.first, regBits.second)];
if (false)
{
std::cerr << "speedMT: " << speedMT << "\n";
Expand Down Expand Up @@ -10090,11 +10090,7 @@ PciHandleType * getDeviceHandle(uint32 vendorId, uint32 deviceId)
const std::vector<MCFGRecord> & mcfg = PciHandleMM::getMCFGRecords();
#else
std::vector<MCFGRecord> mcfg;
MCFGRecord segment;
segment.PCISegmentGroupNumber = 0;
segment.startBusNumber = 0;
segment.endBusNumber = 0xff;
mcfg.push_back(segment);
getMCFGRecords(mcfg);
#endif

for(uint32 s = 0; s < (uint32)mcfg.size(); ++s)
Expand Down Expand Up @@ -10579,11 +10575,11 @@ void PCM::programIDXAccelCounters(uint32 accel, std::vector<uint64_t> &events, s
*ctrl_reg = 0x0;
}

*filter_wq_reg = extract_bits_ui(filters_wq.at(i), 0, 15);
*filter_eng_reg = extract_bits_ui(filters_eng.at(i), 0, 15);
*filter_tc_reg = extract_bits_ui(filters_tc.at(i), 0, 7);
*filter_pgsz_reg = extract_bits_ui(filters_pgsz.at(i), 0, 7);
*filter_xfersz_reg = extract_bits_ui(filters_xfersz.at(i), 0, 7);
*filter_wq_reg = extract_bits_32(filters_wq.at(i), 0, 15);
*filter_eng_reg = extract_bits_32(filters_eng.at(i), 0, 15);
*filter_tc_reg = extract_bits_32(filters_tc.at(i), 0, 7);
*filter_pgsz_reg = extract_bits_32(filters_pgsz.at(i), 0, 7);
*filter_xfersz_reg = extract_bits_32(filters_xfersz.at(i), 0, 7);

if (pmu.getPERFMode() == false)
{
Expand Down
30 changes: 15 additions & 15 deletions src/cpucounters.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -158,13 +158,13 @@ class MMIORegister64 : public HWRegister
}
void operator = (uint64 val) override
{
// std::cout << std::hex << "MMIORegister64 writing " << val << " at offset " << offset << std::dec << std::endl;
DBG(4, std::hex , "MMIORegister64 writing " , val , " at offset " , offset , std::dec);
handle->write64(offset, val);
}
operator uint64 () override
{
const uint64 val = handle->read64(offset);
// std::cout << std::hex << "MMIORegister64 read " << val << " from offset " << offset << std::dec << std::endl;
DBG(4, std::hex , "MMIORegister64 read " , val , " from offset " , offset , std::dec);
return val;
}
};
Expand All @@ -181,13 +181,13 @@ class MMIORegister32 : public HWRegister
}
void operator = (uint64 val) override
{
// std::cout << std::hex << "MMIORegister32 writing " << val << " at offset " << offset << std::dec << std::endl;
DBG(4, std::hex , "MMIORegister32 writing " , val , " at offset " , offset , std::dec);
handle->write32(offset, (uint32)val);
}
operator uint64 () override
{
const uint64 val = (uint64)handle->read32(offset);
// std::cout << std::hex << "MMIORegister32 read " << val << " from offset " << offset << std::dec << std::endl;
DBG(4, std::hex , "MMIORegister32 read " , val , " from offset " , offset , std::dec);
return val;
}
};
Expand All @@ -210,7 +210,7 @@ class MSRRegister : public HWRegister
{
uint64 value = 0;
handle->read(offset, &value);
// std::cout << "reading MSR " << offset << " returning " << value << std::endl;
DBG(4, "reading MSR " , offset , " returning " , value);
return value;
}
};
Expand Down Expand Up @@ -767,7 +767,7 @@ class PCM_API PCM
auto& pmu = pmuIter->second[unit];
for (size_t i = 0; pmu.get() != nullptr && i < pmu->size(); ++i)
{
// std::cerr << "s " << socket << " d " << die << " pmu " << pmu_id << " unit " << unit << " ctr " << i << "\n";
DBG(4, "s " , socket , " d " , die , " pmu " , pmu_id , " unit " , unit , " ctr " , i );
result.Counters[die][pmu_id][unit][i] = *(pmu->counterValue[i]);
}
}
Expand Down Expand Up @@ -3108,7 +3108,7 @@ class BasicCounterState
MemoryBWLocal += o.MemoryBWLocal;
MemoryBWTotal += o.MemoryBWTotal;
SMICount += o.SMICount;
// std::cout << "before PCM debug aggregate "<< FrontendBoundSlots << " " << BadSpeculationSlots << " " << BackendBoundSlots << " " <<RetiringSlots << std::endl;
DBG(4, "before PCM debug aggregate ", FrontendBoundSlots , " " , BadSpeculationSlots , " " , BackendBoundSlots , " " , RetiringSlots );
BasicCounterState old = *this;
FrontendBoundSlots += o.FrontendBoundSlots;
BadSpeculationSlots += o.BadSpeculationSlots;
Expand All @@ -3119,7 +3119,7 @@ class BasicCounterState
FetchLatSlots += o.FetchLatSlots;
BrMispredSlots += o.BrMispredSlots;
HeavyOpsSlots += o.HeavyOpsSlots;
//std::cout << "after PCM debug aggregate "<< FrontendBoundSlots << " " << BadSpeculationSlots << " " << BackendBoundSlots << " " <<RetiringSlots << std::endl;
DBG(4, "after PCM debug aggregate ", FrontendBoundSlots , " " , BadSpeculationSlots , " " , BackendBoundSlots , " " ,RetiringSlots);
assert(FrontendBoundSlots >= old.FrontendBoundSlots);
assert(BadSpeculationSlots >= old.BadSpeculationSlots);
assert(BackendBoundSlots >= old.BackendBoundSlots);
Expand Down Expand Up @@ -5144,7 +5144,7 @@ inline double getLocalMemoryRequestRatio(const CounterStateType & before, const
if (PCM::getInstance()->localMemoryRequestRatioMetricAvailable() == false) return -1.;
const auto all = after.UncHARequests - before.UncHARequests;
const auto local = after.UncHALocalRequests - before.UncHALocalRequests;
// std::cout << "PCM DEBUG "<< 64*all/1e6 << " " << 64*local/1e6 << "\n";
DBG(4, 64*all/1e6 , " " , 64*local/1e6);
return double(local)/double(all);
}

Expand Down Expand Up @@ -5183,8 +5183,8 @@ inline uint64 getAllSlots(const CounterStateType & before, const CounterStateTyp
const int64 b = after.FrontendBoundSlots - before.FrontendBoundSlots;
const int64 c = after.BadSpeculationSlots - before.BadSpeculationSlots;
const int64 d = after.RetiringSlots - before.RetiringSlots;
// std::cout << "before DEBUG: " << before.FrontendBoundSlots << " " << before.BadSpeculationSlots << " "<< before.BackendBoundSlots << " " << before.RetiringSlots << std::endl;
// std::cout << "after DEBUG: " << after.FrontendBoundSlots << " " << after.BadSpeculationSlots << " " << after.BackendBoundSlots << " " << after.RetiringSlots << std::endl;
DBG(4, "before: " , before.FrontendBoundSlots , " " , before.BadSpeculationSlots , " ", before.BackendBoundSlots , " " , before.RetiringSlots);
DBG(4, "afterG: " , after.FrontendBoundSlots , " " , after.BadSpeculationSlots , " " , after.BackendBoundSlots , " " , after.RetiringSlots);
assert(a >= 0);
assert(b >= 0);
assert(c >= 0);
Expand All @@ -5202,7 +5202,7 @@ inline uint64 getAllSlotsRaw(const CounterStateType& before, const CounterStateT
template <class CounterStateType>
inline double getBackendBound(const CounterStateType & before, const CounterStateType & after)
{
// std::cout << "DEBUG: "<< after.BackendBoundSlots - before.BackendBoundSlots << " " << getAllSlots(before, after) << std::endl;
DBG(4, (after.BackendBoundSlots - before.BackendBoundSlots) , " " , getAllSlots(before, after));
if (PCM::getInstance()->isHWTMAL1Supported())
return double(after.BackendBoundSlots - before.BackendBoundSlots)/double(getAllSlots(before, after));
return 0.;
Expand Down Expand Up @@ -5230,7 +5230,7 @@ inline double getCoreBound(const CounterStateType & before, const CounterStateTy
template <class CounterStateType>
inline double getFrontendBound(const CounterStateType & before, const CounterStateType & after)
{
// std::cout << "DEBUG: "<< after.FrontendBoundSlots - before.FrontendBoundSlots << " " << getAllSlots(before, after) << std::endl;
DBG(4, (after.FrontendBoundSlots - before.FrontendBoundSlots) , " " , getAllSlots(before, after));
if (PCM::getInstance()->isHWTMAL1Supported())
return double(after.FrontendBoundSlots - before.FrontendBoundSlots)/double(getAllSlots(before, after));
return 0.;
Expand Down Expand Up @@ -5258,7 +5258,7 @@ inline double getFetchBandwidthBound(const CounterStateType & before, const Coun
template <class CounterStateType>
inline double getBadSpeculation(const CounterStateType & before, const CounterStateType & after)
{
// std::cout << "DEBUG: "<< after.BadSpeculationSlots - before.BadSpeculationSlots << " " << getAllSlots(before, after) << std::endl;
DBG(4, (after.BadSpeculationSlots - before.BadSpeculationSlots) , " " , getAllSlots(before, after));
if (PCM::getInstance()->isHWTMAL1Supported())
return double(after.BadSpeculationSlots - before.BadSpeculationSlots)/double(getAllSlots(before, after));
return 0.;
Expand Down Expand Up @@ -5286,7 +5286,7 @@ inline double getMachineClearsBound(const CounterStateType & before, const Count
template <class CounterStateType>
inline double getRetiring(const CounterStateType & before, const CounterStateType & after)
{
// std::cout << "DEBUG: "<< after.RetiringSlots - before.RetiringSlots << " " << getAllSlots(before, after) << std::endl;
DBG(4, (after.RetiringSlots - before.RetiringSlots) , " " , getAllSlots(before, after));
if (PCM::getInstance()->isHWTMAL1Supported())
return double(after.RetiringSlots - before.RetiringSlots)/double(getAllSlots(before, after));
return 0.;
Expand Down
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