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lialan committed Nov 11, 2024
1 parent a8050a8 commit f623b7f
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Showing 3 changed files with 9 additions and 5 deletions.
10 changes: 7 additions & 3 deletions compiler/src/iree/compiler/Codegen/LLVMCPU/KernelDispatch.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -2918,9 +2918,13 @@ setLoweringConfigForComputeOps(mlir::FunctionOpInterface entryPointFn,
cast<ShapedType>(rootOperation->getResultTypes().front())
.getElementType()
.getIntOrFloatBitWidth();
auto innermostTileSize = commonVecTileSizes.back();
commonVecTileSizes.back() =
llvm::alignTo(innermostTileSize * elementTypeSize, 8) / elementTypeSize;
// for now just enable for i1
if (elementTypeSize == 1) {
auto innermostTileSize = commonVecTileSizes.back();
commonVecTileSizes.back() =
llvm::alignTo(innermostTileSize * elementTypeSize, 8) /
elementTypeSize;
}
}

// Set the lowering configs with new tile sizes.
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Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
// RUN: iree-opt --split-input-file --iree-stream-encode-host-tensors --iree-experimental-packed-i1-storage --verify-diagnostics %s | FileCheck %s
// RUN: iree-opt --split-input-file --iree-stream-encode-host-tensors --verify-diagnostics %s | FileCheck %s

// CHECK-LABEL: util.func public @denseTensorConstantI2()
util.func public @denseTensorConstantI2() -> !stream.resource<constant> {
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2 changes: 1 addition & 1 deletion tests/e2e/subbyte_types/subbyte_types.mlir
Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@ func.func @i1_type() {
ins(%lhs, %rhs : tensor<8xi1>, tensor<8xi1>) outs(%empty: tensor<8xi1>) {
^bb0(%inlhs: i1, %inrhs: i1, %out: i1):
%inres = arith.xori %inlhs, %inrhs: i1
linalg.yield %inres : i1
linalg.yield %inres : i1
} -> tensor<8xi1>
%tensor_res = flow.tensor.bitcast %res : tensor<8xi1> -> tensor<1xi8>
check.expect_eq_const(%tensor_res, dense<[255]> : tensor<1xi8>) : tensor<1xi8>
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