[Codegen][GPU] Add kernel config for LLVMGPUTileAndFuse #17791
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Talked offline, the correctness issues looked to be a floating point precision ghost. I verified e2e correctness of this patch on SDXL int8 by generating an image. |
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I think it is fine to land. There is a similar issue with VectorDistribute fusions, which may be causing minor precision differences. I talked with @MaheshRavishankar and we still want to track this precision difference. Ideally these precision differences should be able to be truned off if necessary to produce bitwise exact results independent of pipelines. Not blocking progress, since numerics are overall accurate, but we should track this.
This adds kernel configuration logic for targeting simple thread distribution of linalg-based dispatches on LLVMGPU. The configuration logic is primarily copied from the same logic on the SPIR-V side due to the already well tested heuristics there for the kinds of varied target descriptions that are present for SPIR-V. Currently this is locked behind a flag `iree-codegen-llvmgpu-use-tile-and-fuse`.
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This adds kernel configuration logic for targeting simple thread distribution of linalg-based dispatches on LLVMGPU. The configuration logic is primarily copied from the same logic on the SPIR-V side due to the already well tested heuristics there for the kinds of varied target descriptions that are present on the SPIR-V side.
Currently this is locked behind a flag
iree-codegen-llvmgpu-use-tile-and-fuse. Future patches will add specialized logic for matmul.