Quartz64: Add fan control settings.

Quartz64 has a fan header controlled by GPIO0_D5 (FAN_CTL_H). This change adds a config menu item for turning the fan on and off. Default value is "on".
jaredmcneill · Apr 16, 2023 · e5c0af0 · e5c0af0
1 parent e1f3e1a
commit e5c0af0
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Showing 7 changed files with 73 additions and 1 deletion.
diff --git a/edk2-rockchip/Platform/Pine64/Quartz64/Quartz64.dsc b/edk2-rockchip/Platform/Pine64/Quartz64/Quartz64.dsc
@@ -473,6 +473,12 @@
   gRk356xTokenSpaceGuid.PcdPciePowerGpioBank|0
   gRk356xTokenSpaceGuid.PcdPciePowerGpioPin|22
 
+  #
+  # Fan support
+  #
+  gRk356xTokenSpaceGuid.PcdFanGpioBank|0
+  gRk356xTokenSpaceGuid.PcdFanGpioPin|27
+
   #
   # This board has inverted polarity for the PWREN pin on the SD card slot
   #
@@ -493,6 +499,7 @@
   gRk356xTokenSpaceGuid.PcdCpuClock|L"CpuClock"|gConfigDxeFormSetGuid|0x0|2
   gRk356xTokenSpaceGuid.PcdCustomCpuClock|L"CustomCpuClock"|gConfigDxeFormSetGuid|0x0|816
   gRk356xTokenSpaceGuid.PcdMultiPhy1Mode|L"MultiPhy1Mode"|gConfigDxeFormSetGuid|0x0|0
+  gRk356xTokenSpaceGuid.PcdFanMode|L"FanMode"|gConfigDxeFormSetGuid|0x0|1
 
   #
   # Common UEFI ones.

diff --git a/edk2-rockchip/Platform/Rockchip/Rk356x/Drivers/ConfigDxe/ConfigDxe.c b/edk2-rockchip/Platform/Rockchip/Rk356x/Drivers/ConfigDxe/ConfigDxe.c
@@ -22,6 +22,7 @@
 #include <Library/UefiRuntimeServicesTableLib.h>
 #include <Library/PcdLib.h>
 #include <Library/CpuVoltageLib.h>
+#include <Library/GpioLib.h>
 #include <Protocol/ArmScmi.h>
 #include <Protocol/ArmScmiClockProtocol.h>
 #include <ConfigVars.h>
@@ -30,6 +31,9 @@
 
 #define CLOCK_ID_CLK_SCMI_CPU     0
 #define FREQ_1_MHZ                1000000
+#define FAN_GPIO_BANK             FixedPcdGet8 (PcdFanGpioBank)
+#define FAN_GPIO_PIN              FixedPcdGet8 (PcdFanGpioPin)
+#define FAN_GPIO_ENABLE_VALUE     FixedPcdGetBool (PcdFanGpioActiveHigh)
 
 extern UINT8 ConfigDxeHiiBin[];
 extern UINT8 ConfigDxeStrings[];
@@ -302,6 +306,18 @@ SetupVariables (
   }
 #endif
 
+#if FAN_GPIO_BANK != 0xFF
+  ASSERT (FAN_GPIO_PIN != 0xFF);
+  Size = sizeof (UINT32);
+  Status = gRT->GetVariable (L"FanMode",
+                             &gConfigDxeFormSetGuid,
+                             NULL, &Size, &Var32);
+  if (EFI_ERROR (Status)) {
+    Status = PcdSet32S (PcdFanMode, PcdGet32 (PcdFanMode));
+    ASSERT_EFI_ERROR (Status);
+  }
+#endif
+
   return EFI_SUCCESS;
 }
 
@@ -317,6 +333,19 @@ ApplyVariables (
   UINT64     SpeedHz;
   UINT64     CurSpeedHz;
 
+#if FAN_GPIO_BANK != 0xFF
+  /*
+   * Fan settings
+   */
+  if (PcdGet32 (PcdFanMode) == FAN_MODE_ON) {
+    GpioPinSetDirection (FAN_GPIO_BANK, FAN_GPIO_PIN, GPIO_PIN_OUTPUT);
+    GpioPinWrite (FAN_GPIO_BANK, FAN_GPIO_PIN, FAN_GPIO_ENABLE_VALUE);
+  }
+#endif
+
+  /*
+   * CPU clock settings
+   */
   switch (CpuClock) {
   case CPUCLOCK_DEFAULT:
     SpeedHz = 0;

diff --git a/edk2-rockchip/Platform/Rockchip/Rk356x/Drivers/ConfigDxe/ConfigDxe.inf b/edk2-rockchip/Platform/Rockchip/Rk356x/Drivers/ConfigDxe/ConfigDxe.inf
@@ -63,12 +63,16 @@
 [Protocols]
 
 [FixedPcd]
+  gRk356xTokenSpaceGuid.PcdFanGpioBank
+  gRk356xTokenSpaceGuid.PcdFanGpioPin
+  gRk356xTokenSpaceGuid.PcdFanGpioActiveHigh
 
 [Pcd]
   gRk356xTokenSpaceGuid.PcdSystemTableMode
   gRk356xTokenSpaceGuid.PcdCpuClock
   gRk356xTokenSpaceGuid.PcdCustomCpuClock
   gRk356xTokenSpaceGuid.PcdMultiPhy1Mode
+  gRk356xTokenSpaceGuid.PcdFanMode
 
 [Depex]
   gPcdProtocolGuid
diff --git a/edk2-rockchip/Platform/Rockchip/Rk356x/Drivers/ConfigDxe/ConfigDxeHii.uni b/edk2-rockchip/Platform/Rockchip/Rk356x/Drivers/ConfigDxe/ConfigDxeHii.uni
@@ -44,4 +44,9 @@
 #string STR_SYSCONFIG_MULTIPHY1_PROMPT   #language en-US "USB3/SATA Selection"
 #string STR_SYSCONFIG_MULTIPHY1_HELP     #language en-US "Enable USB3 or SATA port"
 #string STR_SYSCONFIG_MULTIPHY1_USB3     #language en-US "USB3"
-#string STR_SYSCONFIG_MULTIPHY1_SATA     #language en-US "SATA"
+#string STR_SYSCONFIG_MULTIPHY1_SATA     #language en-US "SATA"
+
+#string STR_SYSCONFIG_FAN_PROMPT   #language en-US "Fan Mode"
+#string STR_SYSCONFIG_FAN_HELP     #language en-US "Settings for GPIO fan"
+#string STR_SYSCONFIG_FAN_ON       #language en-US "Always on"
+#string STR_SYSCONFIG_FAN_OFF      #language en-US "Off"
diff --git a/edk2-rockchip/Platform/Rockchip/Rk356x/Drivers/ConfigDxe/ConfigDxeHii.vfr b/edk2-rockchip/Platform/Rockchip/Rk356x/Drivers/ConfigDxe/ConfigDxeHii.vfr
@@ -48,6 +48,13 @@ formset
       guid  = CONFIGDXE_FORM_SET_GUID;
 #endif
 
+#if FixedPcdGet8 (PcdFanGpioBank) != 0xFF
+    efivarstore MULTIPHY_MODE_VARSTORE_DATA,
+      attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,
+      name  = FanMode,
+      guid  = CONFIGDXE_FORM_SET_GUID;
+#endif
+
     form formid = 1,
         title  = STRING_TOKEN(STR_FORM_SET_TITLE);
         subtitle text = STRING_TOKEN(STR_NULL_STRING);
@@ -98,5 +105,15 @@ formset
             option text = STRING_TOKEN(STR_SYSCONFIG_MULTIPHY1_SATA), value = MULTIPHY_MODE_SEL_SATA, flags = 0;
         endoneof;
 #endif
+
+#if FixedPcdGet8 (PcdFanGpioBank) != 0xFF
+        oneof varid = FanMode.Mode,
+            prompt      = STRING_TOKEN(STR_SYSCONFIG_FAN_PROMPT),
+            help        = STRING_TOKEN(STR_SYSCONFIG_FAN_HELP),
+            flags       = NUMERIC_SIZE_4 | INTERACTIVE | RESET_REQUIRED,
+            option text = STRING_TOKEN(STR_SYSCONFIG_FAN_OFF), value = FAN_MODE_OFF, flags = 0;
+            option text = STRING_TOKEN(STR_SYSCONFIG_FAN_ON), value = FAN_MODE_ON, flags = DEFAULT;
+        endoneof;
+#endif
     endform;
 endformset;
diff --git a/edk2-rockchip/Platform/Rockchip/Rk356x/Include/ConfigVars.h b/edk2-rockchip/Platform/Rockchip/Rk356x/Include/ConfigVars.h
@@ -37,4 +37,10 @@ typedef struct {
   UINT32 Mode;
 } MULTIPHY_MODE_VARSTORE_DATA;
 
+typedef struct {
+#define FAN_MODE_OFF 0
+#define FAN_MODE_ON  1
+  UINT32 Mode;
+} FAN_VARSTORE_DATA;
+
 #endif /* CONFIG_VARS_H */
diff --git a/edk2-rockchip/Platform/Rockchip/Rk356x/Rk356x.dec b/edk2-rockchip/Platform/Rockchip/Rk356x/Rk356x.dec
@@ -53,10 +53,14 @@
   gRk356xTokenSpaceGuid.PcdNvStorageFtwSpareBase|0x0|UINT32|0x00002003
   gRk356xTokenSpaceGuid.PcdNvStorageFtwWorkingBase|0x0|UINT32|0x00002004
   gRk356xTokenSpaceGuid.PcdFdStorageOffset|0x00100000|UINT32|0x00003000
+  gRk356xTokenSpaceGuid.PcdFanGpioBank|0xFF|UINT8|0x00003001
+  gRk356xTokenSpaceGuid.PcdFanGpioPin|0xFF|UINT8|0x00003002
+  gRk356xTokenSpaceGuid.PcdFanGpioActiveHigh|TRUE|BOOLEAN|0x00003003
 
 [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
   gRk356xTokenSpaceGuid.PcdPlatformResetDelay|0|UINT32|0x00004000
   gRk356xTokenSpaceGuid.PcdSystemTableMode|0|UINT32|0x00004001
   gRk356xTokenSpaceGuid.PcdCpuClock|2|UINT32|0x00004002
   gRk356xTokenSpaceGuid.PcdCustomCpuClock|816|UINT32|0x00004003
   gRk356xTokenSpaceGuid.PcdMultiPhy1Mode|0|UINT32|0x00004004
+  gRk356xTokenSpaceGuid.PcdFanMode|0|UINT32|0x00040005