Document and clean up interface of serv_immdec

manihatn · Dec 29, 2020 · ca1a07f · ca1a07f
1 parent 14cbe03
commit ca1a07f
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Showing 5 changed files with 35 additions and 19 deletions.
diff --git a/doc/index.rst b/doc/index.rst
@@ -95,6 +95,17 @@ serv_decode is responsible for decoding the operation word coming from ibus into
 
 .. image:: serv_decode_int.png
 
+serv_immdec
+^^^^^^^^^^^
+
+.. image:: serv_immdec.png
+
+The main responsibility of serv_immdec is to stitch together the pieces of immediates from the instruction word and push it out in the correct order. When a new instruction arrives, the relevant parts are placed into a number of shift registers, and the connections between the registers are setup differently depending on the type of operation.
+
+serv_immdec also extracts the register addresses from the operation word.
+
+.. image:: serv_immdec_int.png
+
 serv_mem_if
 ^^^^^^^^^^^
 

diff --git a/doc/serv_immdec.png b/doc/serv_immdec.png
diff --git a/doc/serv_immdec_int.png b/doc/serv_immdec_int.png
diff --git a/rtl/serv_immdec.v b/rtl/serv_immdec.v
@@ -2,19 +2,21 @@
 module serv_immdec
   (
    input wire 	     i_clk,
-   //Input
+   //State
    input wire 	     i_cnt_en,
-   input wire 	     i_csr_imm_en,
-   output wire 	     o_csr_imm,
-   input wire [31:2] i_wb_rdt,
-   input wire 	     i_wb_en,
    input wire 	     i_cnt_done,
+   //Control
+   input wire 	     i_csr_imm_en,
    input wire [3:0]  i_ctrl,
-   //To RF
    output wire [4:0] o_rd_addr,
    output wire [4:0] o_rs1_addr,
    output wire [4:0] o_rs2_addr,
-   output wire 	     o_imm);
+   //Data
+   output wire 	     o_csr_imm,
+   output wire 	     o_imm,
+   //External
+   input wire 	     i_wb_en,
+   input wire [31:7] i_wb_rdt);
 
    reg 	      signbit;
 

diff --git a/rtl/serv_top.v b/rtl/serv_top.v
@@ -259,19 +259,22 @@ module serv_top
 
    serv_immdec immdec
      (
-      .i_clk      (clk),
-      .i_cnt_en   (cnt_en),
+      .i_clk        (clk),
+      //State
+      .i_cnt_en     (cnt_en),
+      .i_cnt_done   (cnt_done),
+      //Control
       .i_csr_imm_en (csr_imm_en),
-      .o_csr_imm  (csr_imm),
-      .i_wb_rdt   (i_ibus_rdt[31:2]),
-      .i_wb_en    (i_ibus_ack),
-      .i_ctrl     (immdec_ctrl),
-      .i_cnt_done (cnt_done),
-      //To RF
-      .o_rd_addr  (rd_addr),
-      .o_rs1_addr (rs1_addr),
-      .o_rs2_addr (rs2_addr),
-      .o_imm      (imm));
+      .i_ctrl       (immdec_ctrl),
+      .o_rd_addr    (rd_addr),
+      .o_rs1_addr   (rs1_addr),
+      .o_rs2_addr   (rs2_addr),
+      //Data
+      .o_csr_imm    (csr_imm),
+      .o_imm        (imm),
+      //External
+      .i_wb_en      (i_ibus_ack),
+      .i_wb_rdt     (i_ibus_rdt[31:7]));
 
    serv_bufreg bufreg
      (