Fix a few errors which stop this core running through Verilator. #1
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Great thanks! Maybe I should also get a Verilator as soon as possible :P As for the AXI-Stream part, I'm still considering if it's more convenient to keep these AXI-S wrappers and moving DMA to the outside of this core, for it could allow more flexibility on the memory-mapped side, like connecting to DMAs for different buses or different bus widths. |
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