prog_mem.vhd

--Custom defined memory; much simpler than Altera Megafunction.
--Synchronous reads and writes
--Quartus automatically synthesises as RAM (Modelsim doesn't know the difference)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

ENTITY prog_mem IS
	PORT
	(
		clock		: IN STD_LOGIC  := '1';
		data		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
		rdaddress		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
		wraddress		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
		wren		: IN STD_LOGIC  := '0';
		q		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
	);
END prog_mem;

ARCHITECTURE behaviour OF prog_mem IS
	type DMEMORY is array(0 to 65535) of std_logic_vector(15 downto 0); --16K Memory
	constant dataInit : DMEMORY := (
  x"4010",x"0006",x"001A",
  x"4020",x"000A",x"002A",
  x"F821",x"000B",x"002B",
  x"4030",x"00AA",x"0040",
  x"4040",x"0092",x"00F0",
  x"C843",x"00C0",x"000D",
        x"BEEF", --Address 0
        x"1234", --Address 1
		others => x"0000");
	signal DATA_MEM : DMEMORY := dataInit;
BEGIN
	
	memory_access: process(clock)
	begin
		if (clock'event and clock='1') then
			if (wren = '1') then
				DATA_MEM(to_integer(unsigned(wraddress(15 downto 0)))) <= data;
			end if;
				q <= DATA_MEM(to_integer(unsigned(rdaddress(15 downto 0))));
		end if;
	end process memory_access;   
	
END behaviour;