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End of phase 1
End of phase 1
 
 
Endrico - Got everything compiling up to datapath, not CU
Endrico - Got everything compiling up to datapath, not CU
 
 
Endrico - Latest 17 4 2015 PC Mostly Done
Endrico - Latest 17 4 2015 PC Mostly Done
 
 
Endrico - Processor Block
Endrico - Processor Block
 
 
Endrico - Program Counter
Endrico - Program Counter
 
 
Endrico - Working PC
Endrico - Working PC
 
 
Endrico - mostly working jsut need to get it working better
Endrico - mostly working jsut need to get it working better
 
 
Endrico - up to now 24.4.2015
Endrico - up to now 24.4.2015
 
 
Endrico- Data Memory files
Endrico- Data Memory files
 
 
Endrico- Latest 23.4.2015 compiling
Endrico- Latest 23.4.2015 compiling
 
 
New folder
New folder
 
 
PhaseII
PhaseII
 
 
Processor Testbench
Processor Testbench
 
 
mmil111 - assign1
mmil111 - assign1
 
 
.gitignore
.gitignore
 
 
ALU.cpp
ALU.cpp
 
 
ALU.h
ALU.h
 
 
ControlUnit.cpp
ControlUnit.cpp
 
 
ControlUnit.h
ControlUnit.h
 
 
DPRegisters.cpp
DPRegisters.cpp
 
 
DPRegisters.h
DPRegisters.h
 
 
Datapath.cpp
Datapath.cpp
 
 
Datapath.h
Datapath.h
 
 
EOT.cpp
EOT.cpp
 
 
EOT.h
EOT.h
 
 
ER.cpp
ER.cpp
 
 
ER.h
ER.h
 
 
IR.cpp
IR.cpp
 
 
IR.h
IR.h
 
 
MAX.cpp
MAX.cpp
 
 
MAX.h
MAX.h
 
 
Mul2.cpp
Mul2.cpp
 
 
Mul2.h
Mul2.h
 
 
Mul4.cpp
Mul4.cpp
 
 
Mul4.h
Mul4.h
 
 
Mul7.cpp
Mul7.cpp
 
 
Mul7.h
Mul7.h
 
 
PC.h
PC.h
 
 
PC.h.old
PC.h.old
 
 
PCAdder.cpp
PCAdder.cpp
 
 
PCAdder.h
PCAdder.h
 
 
README.md
README.md
 
 
RF.cpp
RF.cpp
 
 
RF.h
RF.h
 
 
Register.cpp
Register.cpp
 
 
Register.h
Register.h
 
 
data_mem.h
data_mem.h
 
 
data_mem.vhd
data_mem.vhd
 
 
modelsim.ini
modelsim.ini
 
 
pc_tb.cpp
pc_tb.cpp
 
 
pc_tb.h
pc_tb.h
 
 
processor.h
processor.h
 
 
prog_mem.h
prog_mem.h
 
 
prog_mem.vhd
prog_mem.vhd
 
 

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CS701Proj

Compsys 701 group project

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Compsys 701 group project

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  • C++ 74.0%
  • VHDL 15.6%
  • C 4.1%
  • Stata 3.7%
  • Makefile 1.6%
  • Python 0.9%
  • Assembly 0.1%