Merge pull request #81 from ivq/up_add_wifi

Add Wi-Fi support

board/pine64/ox64/patches/linux/0029-bl808-Add-M0-firmware-loader.patch

@@ -0,0 +1,184 @@
+From 986b23041540d94bae1a51f94e25c6b8bc769d3d Mon Sep 17 00:00:00 2001
+From: qwang <[email protected]>
+Date: Thu, 14 Sep 2023 14:21:23 +0800
+Subject: [PATCH] bl808: Add M0 firmware loader
+
+Signed-off-by: qwang <[email protected]>
+---
+ drivers/firmware/Makefile           |   1 +
+ drivers/firmware/bflb-m0-fw.c       | 129 ++++++++++++++++++++++++++++
+ include/linux/firmware/bflb-m0-fw.h |  14 +++
+ 3 files changed, 144 insertions(+)
+ create mode 100644 drivers/firmware/bflb-m0-fw.c
+ create mode 100644 include/linux/firmware/bflb-m0-fw.h
+
+diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
+index 28fcddcd6..93983ea6b 100644
+--- a/drivers/firmware/Makefile
++++ b/drivers/firmware/Makefile
+@@ -25,6 +25,7 @@ obj-$(CONFIG_SYSFB_SIMPLEFB)	+= sysfb_simplefb.o
+ obj-$(CONFIG_TI_SCI_PROTOCOL)	+= ti_sci.o
+ obj-$(CONFIG_TRUSTED_FOUNDATIONS) += trusted_foundations.o
+ obj-$(CONFIG_TURRIS_MOX_RWTM)	+= turris-mox-rwtm.o
++obj-$(CONFIG_SOC_BOUFFALOLAB)	+= bflb-m0-fw.o
+
+ obj-y				+= arm_ffa/
+ obj-y				+= arm_scmi/
+diff --git a/drivers/firmware/bflb-m0-fw.c b/drivers/firmware/bflb-m0-fw.c
+new file mode 100644
+index 000000000..d3991af07
+--- /dev/null
++++ b/drivers/firmware/bflb-m0-fw.c
+@@ -0,0 +1,129 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * Helpers for loading firmware/resetting M0 on BL808.
++ *
++ * Copyright (C) Bouffalo Lab 2016-2023
++ */
++
++#include <linux/firmware/bflb-m0-fw.h>
++#include <linux/delay.h>
++#include <linux/io.h>
++
++#define GLB_BASE 0x20000000
++#define PDS_BASE 0x2000e000
++
++#define PDS_CPU_CORE_CFG1_OFFSET	(0x114)
++#define PDS_REG_MCU1_CLK_EN_POS		(8U)
++#define PDS_CPU_CORE_CFG14_OFFSET	(0x148)
++
++#define GLB_SWRST_CFG2_OFFSET		(0x548)
++#define GLB_REG_CTRL_CPU_RESET_POS	(1U)
++
++int bflb_halt_m0(void)
++{
++	int ret = 0;
++	u8 __iomem *glb_base = NULL;
++	u8 __iomem *pds_base = NULL;
++	u32 tmp;
++
++	if ((glb_base = ioremap(GLB_BASE, 0x1000)) == NULL ||
++			(pds_base = ioremap(PDS_BASE, 0x1000)) == NULL) {
++		ret = -ENOMEM;
++		goto cleanup;
++	}
++
++	/* disable M0 clock */
++	tmp = readl(pds_base + PDS_CPU_CORE_CFG1_OFFSET);
++	tmp &= ~BIT(PDS_REG_MCU1_CLK_EN_POS);
++	writel(tmp, pds_base + PDS_CPU_CORE_CFG1_OFFSET);
++	udelay(1);
++	/* reset CPU */
++	tmp = readl(glb_base + GLB_SWRST_CFG2_OFFSET);
++	tmp |= BIT(GLB_REG_CTRL_CPU_RESET_POS);
++	writel(tmp, glb_base + GLB_SWRST_CFG2_OFFSET);
++
++cleanup:
++	if (glb_base)
++		iounmap(glb_base);
++	if (pds_base)
++		iounmap(pds_base);
++
++	return ret;
++}
++EXPORT_SYMBOL_GPL(bflb_halt_m0);
++
++int bflb_reset_m0(u32 reset_addr)
++{
++	int ret = 0;
++	u8 __iomem *glb_base = NULL;
++	u8 __iomem *pds_base = NULL;
++	u32 tmp;
++
++	if ((glb_base = ioremap(GLB_BASE, 0x1000)) == NULL ||
++			(pds_base = ioremap(PDS_BASE, 0x1000)) == NULL) {
++		ret = -ENOMEM;
++		goto cleanup;
++	}
++
++	/* set reset address */
++	writel(reset_addr, pds_base + PDS_CPU_CORE_CFG14_OFFSET);
++	/* enable M0 clock */
++	tmp = readl(pds_base + PDS_CPU_CORE_CFG1_OFFSET);
++	tmp |= BIT(PDS_REG_MCU1_CLK_EN_POS);
++	writel(tmp, pds_base + PDS_CPU_CORE_CFG1_OFFSET);
++	udelay(1);
++	/* reset CPU */
++	tmp = readl(glb_base + GLB_SWRST_CFG2_OFFSET);
++	tmp |= BIT(GLB_REG_CTRL_CPU_RESET_POS);
++	writel(tmp, glb_base + GLB_SWRST_CFG2_OFFSET);
++
++cleanup:
++	if (glb_base)
++		iounmap(glb_base);
++	if (pds_base)
++		iounmap(pds_base);
++
++	return ret;
++}
++EXPORT_SYMBOL_GPL(bflb_reset_m0);
++
++int bflb_load_m0_fw(struct device *dev, const char *fwname, u32 load_address)
++{
++	const struct firmware *fw;
++	int ret = 0;
++	u8 __iomem *tgt = NULL;
++
++	ret = request_firmware(&fw, fwname, dev);
++	if (ret) {
++		dev_err(dev, "Request firmware failed\n");
++		return ret;
++	}
++
++	if ((tgt = ioremap(load_address, fw->size)) == NULL) {
++		ret = -ENOMEM;
++		goto cleanup;
++	}
++
++	/* copy fw */
++	memcpy_toio(tgt, fw->data, fw->size);
++
++cleanup:
++	if (tgt)
++		iounmap(tgt);
++	release_firmware(fw);
++
++	return ret;
++}
++EXPORT_SYMBOL_GPL(bflb_load_m0_fw);
++
++int bflb_run_m0_fw(struct device *dev, const char *fwname, u32 load_address)
++{
++	int ret;
++
++	if ((ret = bflb_halt_m0()))
++		return ret;
++	if ((ret = bflb_load_m0_fw(dev, fwname, load_address)))
++		return ret;
++	return bflb_reset_m0(load_address);
++}
++EXPORT_SYMBOL_GPL(bflb_run_m0_fw);
+diff --git a/include/linux/firmware/bflb-m0-fw.h b/include/linux/firmware/bflb-m0-fw.h
+new file mode 100644
+index 000000000..ab415b197
+--- /dev/null
++++ b/include/linux/firmware/bflb-m0-fw.h
+@@ -0,0 +1,14 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * Helpers for loading firmware/resetting M0 on BL808.
++ *
++ * Copyright (C) Bouffalo Lab 2016-2023
++ */
++
++#include <linux/device.h>
++#include <linux/firmware.h>
++
++int bflb_halt_m0(void);
++int bflb_reset_m0(u32 reset_addr);
++int bflb_load_m0_fw(struct device *dev, const char *fwname, u32 load_address);
++int bflb_run_m0_fw(struct device *dev, const char *fwname, u32 load_address);
+-- 
+2.42.0
+

board/pine64/ox64/patches/linux/0030-dts-bl808-reserve-1M-memory-for-M0-fw.patch

@@ -0,0 +1,59 @@
+From a70feac1e381ac82d259ffee4c7d32ec60f5429d Mon Sep 17 00:00:00 2001
+From: qwang <[email protected]>
+Date: Fri, 24 Nov 2023 11:08:20 +0800
+Subject: [PATCH] dts: bl808: reserve 1M memory for M0 fw
+
+Signed-off-by: qwang <[email protected]>
+---
+ .../riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts | 11 +++++++++++
+ arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts | 12 ++++++++++++
+ 2 files changed, 23 insertions(+)
+
+diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts b/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts
+index e5c291471..c22760b88 100644
+--- a/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts
++++ b/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts
+@@ -28,6 +28,17 @@ memory@50000000 {
+ 		reg = <0x50000000 0x04000000>;
+ 	};
+
++	reserved-memory {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges;
++
++		m0_psram_reserved: m0_psram@53F00000 {
++			reg = <0x53F00000 0x100000>;
++			status = "okay";
++		};
++	};
++
+ 	xip_flash@58500000 {
+ 		compatible = "mtd-rom";
+ 		reg = <0x58500000 0x400000>;
+diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts
+index f713d468c..29f1c0323 100644
+--- a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts
++++ b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts
+@@ -29,6 +29,18 @@ memory@50000000 {
+ 		reg = <0x50000000 0x04000000>;
+ 	};
+
++	reserved-memory {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges;
++
++		m0_psram_reserved: m0_psram@53F00000 {
++			reg = <0x53F00000 0x100000>;
++			status = "okay";
++		};
++	};
++
++
+ 	xip_flash@58500000 {
+ 		compatible = "mtd-rom";
+ 		reg = <0x58500000 0x400000>;
+-- 
+2.42.1
+

board/pine64/ox64/patches/linux/0031-dts-bl808-add-IPC-node.patch

@@ -0,0 +1,30 @@
+From 3b8d55fc367e204ff049318de27f020c0f1eb8d6 Mon Sep 17 00:00:00 2001
+From: qwang <[email protected]>
+Date: Fri, 24 Nov 2023 14:09:32 +0800
+Subject: [PATCH] dts: bl808: add IPC node
+
+Signed-off-by: qwang <[email protected]>
+---
+ arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi
+index 091048440..597fe2e39 100644
+--- a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi
++++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi
+@@ -148,6 +148,12 @@ plic: interrupt-controller@e0000000 {
+ 			riscv,ndev = <82>;
+ 		};
+
++		ipc {
++			compatible = "bflb-ipc";
++			interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; /* IPC #54 */
++			status = "okay";
++		};
++
+ 		clint: timer@e4000000 {
+ 			compatible = "thead,c900-clint";
+ 			reg = <0xe4000000 0xc000>;
+-- 
+2.42.1
+

board/pine64/ox64/patches/uboot/0003-bl808-dts-Reserve-M0-fw-memory.patch

@@ -0,0 +1,40 @@
+From e61d86f357314bed72ebe4997dc6496998ca86db Mon Sep 17 00:00:00 2001
+From: qwang <[email protected]>
+Date: Fri, 15 Sep 2023 17:04:52 +0800
+Subject: [PATCH] bl808: dts: Reserve M0 fw memory
+
+Signed-off-by: qwang <[email protected]>
+---
+ arch/riscv/dts/bl808-d0-ox64-u-boot.dtsi | 2 +-
+ arch/riscv/dts/bl808-m0-ox64-u-boot.dtsi | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/riscv/dts/bl808-d0-ox64-u-boot.dtsi b/arch/riscv/dts/bl808-d0-ox64-u-boot.dtsi
+index ab2fcd3c32..7d1e594968 100644
+--- a/arch/riscv/dts/bl808-d0-ox64-u-boot.dtsi
++++ b/arch/riscv/dts/bl808-d0-ox64-u-boot.dtsi
+@@ -1,7 +1,7 @@
+ / {
+ 	memory {
+ 		device_type = "memory";
+-		reg = <0x50000000 0x4000000>;
++		reg = <0x50000000 0x3F00000>;
+ 	};
+ };
+
+diff --git a/arch/riscv/dts/bl808-m0-ox64-u-boot.dtsi b/arch/riscv/dts/bl808-m0-ox64-u-boot.dtsi
+index 3b17c4c7a1..20ad56293a 100644
+--- a/arch/riscv/dts/bl808-m0-ox64-u-boot.dtsi
++++ b/arch/riscv/dts/bl808-m0-ox64-u-boot.dtsi
+@@ -1,7 +1,7 @@
+ / {
+ 	memory {
+ 		device_type = "memory";
+-		reg = <0x50000000 0x4000000>;
++		reg = <0x50000000 0x3F00000>;
+ 	};
+ };
+
+-- 
+2.42.0
+

configs/pine64_ox64_defconfig

@@ -112,4 +112,5 @@ BR2_PACKAGE_HOST_UBOOT_TOOLS=y
 BR2_PACKAGE_HOST_UBOOT_TOOLS_FIT_SUPPORT=y
 BR2_PACKAGE_HOST_UBOOT_TOOLS_BOOT_SCRIPT=y
 BR2_PACKAGE_HOST_UBOOT_TOOLS_BOOT_SCRIPT_SOURCE="$(BR2_EXTERNAL_BOUFFALO_BR_PATH)/board/pine64/ox64/boot-pine64.cmd"
+BR2_PACKAGE_BLWNET_XRAM=y
 BR2_PACKAGE_CLOUDUTILS=y

configs/pine64_ox64_full_defconfig

@@ -214,4 +214,5 @@ BR2_PACKAGE_HOST_UBOOT_TOOLS=y
 BR2_PACKAGE_HOST_UBOOT_TOOLS_FIT_SUPPORT=y
 BR2_PACKAGE_HOST_UBOOT_TOOLS_BOOT_SCRIPT=y
 BR2_PACKAGE_HOST_UBOOT_TOOLS_BOOT_SCRIPT_SOURCE="$(BR2_EXTERNAL_BOUFFALO_BR_PATH)/board/pine64/ox64/boot-pine64.cmd"
+BR2_PACKAGE_BLWNET_XRAM=y
 BR2_PACKAGE_CLOUDUTILS=y

package/Config.in

@@ -1 +1,2 @@
-source "$BR2_EXTERNAL_BOUFFALO_BR_PATH/package/cloudutils/Config.in"
+source "$BR2_EXTERNAL_BOUFFALO_BR_PATH/package/cloudutils/Config.in"
+source "$BR2_EXTERNAL_BOUFFALO_BR_PATH/package/blwnet_xram/Config.in"

package/blwnet_xram/Config.in

@@ -0,0 +1,8 @@
+comment "blwnet_xram needs a Linux kernel to be built"
+	depends on !BR2_LINUX_KERNEL
+
+config BR2_PACKAGE_BLWNET_XRAM
+	bool "blwnet_xram"
+	depends on BR2_LINUX_KERNEL
+	help
+	  blwnet_xram for BL808

package/blwnet_xram/blwnet_xram.mk

@@ -0,0 +1,32 @@
+################################################################################
+#
+# blwnet_xram
+#
+################################################################################
+
+BLWNET_XRAM_VERSION = d133be8588f46e7b48d8a43ba157fc8d40797288
+BLWNET_XRAM_SITE = $(call github,bouffalolab,blwnet_xram,$(BLWNET_XRAM_VERSION))
+BLWNET_XRAM_LICENSE = GPL-2.0(kernel driver), Apache 2.0(userspace)
+
+BLWNET_XRAM_MODULE_MAKE_OPTS = \
+	CONFIG_BL_INTF=XRAM
+
+define BLWNET_XRAM_LINUX_CONFIG_FIXUPS
+	$(call KCONFIG_ENABLE_OPT,CONFIG_NET)
+endef
+
+define BLWNET_XRAM_BUILD_CMDS
+	$(TARGET_CONFIGURE_OPTS) $(MAKE) -C $(@D)/userspace
+endef
+
+BLWRET_XRAM_USERSPACE_INSTALL_FILES = blctl sta.sh blctld ap.sh
+
+define BLWNET_XRAM_INSTALL_TARGET_CMDS
+	$(foreach f,$(BLWRET_XRAM_USERSPACE_INSTALL_FILES),\
+		$(INSTALL) -D -m 0755 $(@D)/userspace/$(f) $(TARGET_DIR)/usr/bin
+	)
+	$(INSTALL) -D -m 644 $(@D)/fw/bl808-m0-fh.bin $(TARGET_DIR)/lib/firmware/bl808-m0-fh.bin
+endef
+
+$(eval $(kernel-module))
+$(eval $(generic-package))