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Merge pull request #190 from btsouts/issue-169
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Issue 169
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@phillipstanleymarbell
phillipstanleymarbell authored Dec 11, 2020
2 parents c8da858 + eb7f9a3 commit c2867f8
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Showing 6 changed files with 360 additions and 67 deletions.
219 changes: 153 additions & 66 deletions sim/decode-riscv.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,7 @@
extern int riscv_instr_latencies[][5];
extern char * riscv_opstrs[];


void
riscvdecode(Engine * E, State * S, uint32_t instr, RiscvPipestage * stage)
{
Expand Down Expand Up @@ -326,15 +327,15 @@ riscvdecode(Engine * E, State * S, uint32_t instr, RiscvPipestage * stage)

break;
}
case 0b0110011:
case 0b0110011:
{
switch(tmp->funct3)
switch(tmp->funct7)
{
case 0b000:
case 0b0000000:
{
switch(tmp->funct7)
switch(tmp->funct3)
{
case 0b0000000:
case 0b000:
{
stage->fptr = (void *) riscv_add;
stage->format = INSTR_R;
Expand All @@ -343,73 +344,91 @@ riscvdecode(Engine * E, State * S, uint32_t instr, RiscvPipestage * stage)

break;
}
case 0b0100000:
case 0b001:
{
stage->fptr = (void *) riscv_sub;
stage->fptr = (void *) riscv_sll;
stage->format = INSTR_R;
stage->op = RISCV_OP_SUB;
stage->instr_latencies = (int *)(&riscv_instr_latencies[RISCV_OP_SUB]);
stage->op = RISCV_OP_SLL;
stage->instr_latencies = (int *)(&riscv_instr_latencies[RISCV_OP_SLL]);

break;
}
default:
case 0b010:
{
stage->fptr = (void *) riscv_slt;
stage->format = INSTR_R;
stage->op = RISCV_OP_SLT;
stage->instr_latencies = (int *)(&riscv_instr_latencies[RISCV_OP_SLT]);

break;
}
}
case 0b011:
{
stage->fptr = (void *) riscv_sltu;
stage->format = INSTR_R;
stage->op = RISCV_OP_SLTU;
stage->instr_latencies = (int *)(&riscv_instr_latencies[RISCV_OP_SLTU]);

break;
}
case 0b001:
{
stage->fptr = (void *) riscv_sll;
stage->format = INSTR_R;
stage->op = RISCV_OP_SLL;
stage->instr_latencies = (int *)(&riscv_instr_latencies[RISCV_OP_SLL]);
break;
}
case 0b100:
{
stage->fptr = (void *) riscv_xor;
stage->format = INSTR_R;
stage->op = RISCV_OP_XOR;
stage->instr_latencies = (int *)(&riscv_instr_latencies[RISCV_OP_XOR]);

break;
}
case 0b010:
{
stage->fptr = (void *) riscv_slt;
stage->format = INSTR_R;
stage->op = RISCV_OP_SLT;
stage->instr_latencies = (int *)(&riscv_instr_latencies[RISCV_OP_SLT]);
break;
}
case 0b101:
{
stage->fptr = (void *) riscv_srl;
stage->format = INSTR_R;
stage->op = RISCV_OP_SRL;
stage->instr_latencies = (int *)(&riscv_instr_latencies[RISCV_OP_SRL]);

break;
}
case 0b011:
{
stage->fptr = (void *) riscv_sltu;
stage->format = INSTR_R;
stage->op = RISCV_OP_SLTU;
stage->instr_latencies = (int *)(&riscv_instr_latencies[RISCV_OP_SLTU]);
break;
}
case 0b110:
{
stage->fptr = (void *) riscv_or;
stage->format = INSTR_R;
stage->op = RISCV_OP_OR;
stage->instr_latencies = (int *)(&riscv_instr_latencies[RISCV_OP_OR]);

break;
}
case 0b100:
{
stage->fptr = (void *) riscv_xor;
stage->format = INSTR_R;
stage->op = RISCV_OP_XOR;
stage->instr_latencies = (int *)(&riscv_instr_latencies[RISCV_OP_XOR]);
break;
}
case 0b111:
{
stage->fptr = (void *) riscv_and;
stage->format = INSTR_R;
stage->op = RISCV_OP_AND;
stage->instr_latencies = (int *)(&riscv_instr_latencies[RISCV_OP_AND]);

break;
break;
}
default:
{
break;
}
}

break;
}
case 0b101:
case 0b0100000:
{
switch(tmp->funct7)
switch(tmp->funct3)
{
case 0b0000000:
case 0b000:
{
stage->fptr = (void *) riscv_srl;
stage->fptr = (void *) riscv_sub;
stage->format = INSTR_R;
stage->op = RISCV_OP_SRL;
stage->instr_latencies = (int *)(&riscv_instr_latencies[RISCV_OP_SRL]);
stage->op = RISCV_OP_SUB;
stage->instr_latencies = (int *)(&riscv_instr_latencies[RISCV_OP_SUB]);

break;
}
case 0b0100000:
case 0b101:
{
stage->fptr = (void *) riscv_sra;
stage->format = INSTR_R;
Expand All @@ -420,37 +439,105 @@ riscvdecode(Engine * E, State * S, uint32_t instr, RiscvPipestage * stage)
}
default:
{
fprintf(stderr, "tmp->funct3 0x%X with opcode 0x%X is ignored\n", tmp->funct3, tmp->opcode);
break;
}
}

break;
}
case 0b110:
case 0b0000001: /* RV32M Standard Extension */
{
stage->fptr = (void *) riscv_or;
stage->format = INSTR_R;
stage->op = RISCV_OP_OR;
stage->instr_latencies = (int *)(&riscv_instr_latencies[RISCV_OP_OR]);
switch(tmp->funct3)
{
case 0b000:
{
stage->fptr = (void *) riscv_mul;
stage->format = INSTR_R;
stage->op = RISCV_OP_MUL;
stage->instr_latencies = (int *)(&riscv_instr_latencies[RISCV_OP_MUL]);

break;
}
case 0b111:
{
stage->fptr = (void *) riscv_and;
stage->format = INSTR_R;
stage->op = RISCV_OP_AND;
stage->instr_latencies = (int *)(&riscv_instr_latencies[RISCV_OP_AND]);
break;
}
case 0b001:
{
stage->fptr = (void *) riscv_mulh;
stage->format = INSTR_R;
stage->op = RISCV_OP_MULH;
stage->instr_latencies = (int *)(&riscv_instr_latencies[RISCV_OP_MULH]);

break;
}
case 0b010:
{
stage->fptr = (void *) riscv_mulhsu;
stage->format = INSTR_R;
stage->op = RISCV_OP_MULHSU;
stage->instr_latencies = (int *)(&riscv_instr_latencies[RISCV_OP_MULHSU]);

break;
}
case 0b011:
{
stage->fptr = (void *) riscv_mulhu;
stage->format = INSTR_R;
stage->op = RISCV_OP_MULHU;
stage->instr_latencies = (int *)(&riscv_instr_latencies[RISCV_OP_MULHU]);

break;
}
case 0b100:
{
stage->fptr = (void *) riscv_div;
stage->format = INSTR_R;
stage->op = RISCV_OP_DIV;
stage->instr_latencies = (int *)(&riscv_instr_latencies[RISCV_OP_DIV]);

break;
}
case 0b101:
{
stage->fptr = (void *) riscv_divu;
stage->format = INSTR_R;
stage->op = RISCV_OP_DIVU;
stage->instr_latencies = (int *)(&riscv_instr_latencies[RISCV_OP_DIVU]);

break;
}
case 0b110:
{
stage->fptr = (void *) riscv_rem;
stage->format = INSTR_R;
stage->op = RISCV_OP_REM;
stage->instr_latencies = (int *)(&riscv_instr_latencies[RISCV_OP_REM]);

break;
}
case 0b111:
{
stage->fptr = (void *) riscv_remu;
stage->format = INSTR_R;
stage->op = RISCV_OP_REMU;
stage->instr_latencies = (int *)(&riscv_instr_latencies[RISCV_OP_REMU]);

break;
}
default:
{
break;
}
}

break;
}

default:
{
fprintf(stderr, "tmp->funct7 0x%X with opcode 0x%X is ignored\n", tmp->funct7, tmp->opcode);
break;
}
}


break;
}
case 0b0001111:
Expand Down Expand Up @@ -1307,7 +1394,7 @@ riscvdecode(Engine * E, State * S, uint32_t instr, RiscvPipestage * stage)
{
mprint(E, S, nodeinfo, "Instruction with opcode 0x%X is ignored\n", tmp->opcode);
//sfatal(E, S, "Illegal instruction seen during decode...");

break;
}
}
Expand Down
8 changes: 8 additions & 0 deletions sim/decode-riscv.h
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Original file line number Diff line number Diff line change
Expand Up @@ -48,6 +48,14 @@ enum
RISCV_OP_CSRRWI,
RISCV_OP_CSRRSI,
RISCV_OP_CSRRCI,
RISCV_OP_MUL,
RISCV_OP_MULH,
RISCV_OP_MULHSU,
RISCV_OP_MULHU,
RISCV_OP_DIV,
RISCV_OP_DIVU,
RISCV_OP_REM,
RISCV_OP_REMU,

RISCV_OP_MAX,

Expand Down
8 changes: 8 additions & 0 deletions sim/latencies-riscv.h
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Original file line number Diff line number Diff line change
Expand Up @@ -86,6 +86,14 @@ int riscv_instr_latencies[][5] =\
[RISCV_OP_CSRRWI] {1, 1, 1, 1, 1},
[RISCV_OP_CSRRSI] {1, 1, 1, 1, 1},
[RISCV_OP_CSRRCI] {1, 1, 1, 1, 1},
[RISCV_OP_MUL] {1, 1, 1, 1, 1},
[RISCV_OP_MULH] {1, 1, 1, 1, 1},
[RISCV_OP_MULHSU] {1, 1, 1, 1, 1},
[RISCV_OP_MULHU] {1, 1, 1, 1, 1},
[RISCV_OP_DIV] {1, 1, 1, 1, 1},
[RISCV_OP_DIVU] {1, 1, 1, 1, 1},
[RISCV_OP_REM] {1, 1, 1, 1, 1},
[RISCV_OP_REMU] {1, 1, 1, 1, 1},
/*[RISCV_OP_MAX] square brackets are necessary */
/* RV32F */
[RV32F_OP_FLW] {1, 1, 1, 1, 1},
Expand Down
1 change: 1 addition & 0 deletions sim/main.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -770,6 +770,7 @@ load_mapfile(Engine *E, State *S, char *filename)
else
{
mprint(E, S, nodeinfo, "Unknown memory length %zu in mmap file.\n", strlen(p));

return;
}

Expand Down
12 changes: 12 additions & 0 deletions sim/mfns.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -798,6 +798,18 @@ void riscv_csrrwi(Engine *E, State *S);
void riscv_csrrsi(Engine *E, State *S);
void riscv_csrrci(Engine *E, State *S);

/* */
/* RISC-V RV32M additional functions */
/* */
void riscv_mul(Engine *E, State *S, uint8_t rs1, uint8_t rs2, uint8_t rd);
void riscv_mulh(Engine *E, State *S, uint8_t rs1, uint8_t rs2, uint8_t rd);
void riscv_mulhsu(Engine *E, State *S, uint8_t rs1, uint8_t rs2, uint8_t rd);
void riscv_mulhu(Engine *E, State *S, uint8_t rs1, uint8_t rs2, uint8_t rd);
void riscv_div(Engine *E, State *S, uint8_t rs1, uint8_t rs2, uint8_t rd);
void riscv_divu(Engine *E, State *S, uint8_t rs1, uint8_t rs2, uint8_t rd);
void riscv_rem(Engine *E, State *S, uint8_t rs1, uint8_t rs2, uint8_t rd);
void riscv_remu(Engine *E, State *S, uint8_t rs1, uint8_t rs2, uint8_t rd);

/* */
/* RISC-V RV32F additional functions */
/* */
Expand Down
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