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stage0 HAL: shuffle code that reads/writes MSRs to the HAL.
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This is mostly just copying code around as the original implementation
was fairly generic to begin with.

Bug: 350496083
Change-Id: Ia70d5f10db6aee1cca041482ae081bd0d601b2b8
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andrisaar committed Jul 26, 2024
1 parent 589d8fd commit df0cfab
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Showing 5 changed files with 89 additions and 45 deletions.
1 change: 1 addition & 0 deletions stage0/src/hal/base/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -19,3 +19,4 @@ mod mmio;

pub use cpuid::*;
pub use mmio::*;
pub use x86_64::registers::model_specific::Msr;
41 changes: 41 additions & 0 deletions stage0/src/hal/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -86,3 +86,44 @@ pub fn cpuid(leaf: u32) -> CpuidResult {
#[cfg(not(feature = "sev"))]
return base::cpuid(leaf);
}
/// Wrapper that can access a MSR either directly or through the GHCB, depending
/// on the environment.
pub struct Msr {
#[cfg(feature = "sev")]
msr_id: u32,
msr: base::Msr,
}

impl Msr {
pub const fn new(reg: u32) -> Self {
Self {
#[cfg(feature = "sev")]
msr_id: reg,
msr: base::Msr::new(reg),
}
}

/// Read the MSR.
///
/// ## Safety
///
/// The caller must guarantee that the MSR is valid.
pub unsafe fn read(&self) -> u64 {
#[cfg(feature = "sev")]
return sev::read_msr(&self.msr, self.msr_id);
#[cfg(not(feature = "sev"))]
return self.msr.read();
}

/// Write the MSR.
///
/// ## Safety
///
/// The caller must guarantee that the MSR is valid.
pub unsafe fn write(&mut self, val: u64) {
#[cfg(feature = "sev")]
return sev::write_msr(&mut self.msr, self.msr_id, val);
#[cfg(not(feature = "sev"))]
return self.msr.write(val);
}
}
2 changes: 2 additions & 0 deletions stage0/src/hal/sev/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -16,6 +16,8 @@

mod cpuid;
mod mmio;
mod msr;

pub use cpuid::*;
pub use mmio::*;
pub use msr::*;
43 changes: 43 additions & 0 deletions stage0/src/hal/sev/msr.rs
Original file line number Diff line number Diff line change
@@ -0,0 +1,43 @@
//
// Copyright 2024 The Project Oak Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//

use crate::sev::GHCB_WRAPPER;

/// Read a MSR.
///
/// ## Safety
///
/// The caller must guarantee that the MSR is valid.
pub unsafe fn read_msr(msr: &crate::hal::base::Msr, msr_id: u32) -> u64 {
if let Some(ghcb) = GHCB_WRAPPER.get() {
ghcb.lock().msr_read(msr_id).expect("couldn't read the MSR using the GHCB protocol")
} else {
msr.read()
}
}

/// Write to a MSR.
///
/// ## Safety
///
/// The caller must guarantee that the MSR is valid.
pub unsafe fn write_msr(msr: &mut crate::hal::base::Msr, msr_id: u32, val: u64) {
if let Some(ghcb) = GHCB_WRAPPER.get() {
ghcb.lock().msr_write(msr_id, val).expect("couldn't write the MSR using the GHCB protocol")
} else {
msr.write(val)
}
}
47 changes: 2 additions & 45 deletions stage0/src/msr.rs
Original file line number Diff line number Diff line change
Expand Up @@ -16,52 +16,9 @@

use bitflags::bitflags;
use strum::FromRepr;
use x86_64::{registers::model_specific::Msr as DirectMsr, PhysAddr};
use x86_64::PhysAddr;

use crate::sev::GHCB_WRAPPER;

/// Wrapper that can access a MSR either directly or through the GHCB, depending
/// on the environment.
pub struct Msr {
msr_id: u32,
msr: DirectMsr,
}

impl Msr {
pub const fn new(reg: u32) -> Self {
Self { msr_id: reg, msr: DirectMsr::new(reg) }
}

/// Read the MSR.
///
/// ## Safety
///
/// The caller must guarantee that the MSR is valid.
pub unsafe fn read(&self) -> u64 {
if let Some(ghcb) = GHCB_WRAPPER.get() {
ghcb.lock()
.msr_read(self.msr_id)
.expect("couldn't read the MSR using the GHCB protocol")
} else {
self.msr.read()
}
}

/// Write the MSR.
///
/// ## Safety
///
/// The caller must guarantee that the MSR is valid.
pub unsafe fn write(&mut self, val: u64) {
if let Some(ghcb) = GHCB_WRAPPER.get() {
ghcb.lock()
.msr_write(self.msr_id, val)
.expect("couldn't write the MSR using the GHCB protocol")
} else {
self.msr.write(val)
}
}
}
use crate::hal::Msr;

bitflags! {
/// Flags in the APIC Base Address Register (MSR 0x1B)
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