fix(data_decoding): update scripts

benchmarks/tapa_flow/orcDecoder/Makefile

@@ -3,8 +3,8 @@
 
 ROOT_DIR         := $(shell git rev-parse --show-toplevel)
 KERNEL_NAME      := data_decoding
-RS_SCRIPT        := $(CURDIR)/run.py
-AB_CONFIG        := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/ab_config.json
+RS_SCRIPT        := $(CURDIR)/run_u55c.py
+AB_CONFIG        := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/floorplan_config.json
 IMPL_CONFIG      := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/impl_config.json
 LINK_CONFIG      := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/link_config.ini
 PLATFORM         := xilinx_u55c_gen3x16_xdma_3_202210_1
@@ -26,21 +26,22 @@ all: $(RS_TARGET)
 	cd $(RSPATH) && $(RSPYTHON)	$(SLACK_GETTER) -d $(TEMP_DIR) -i $(TIMING_RPT) -o $(BUILD_LOG)  -c clk_kernel_00_unbuffered_net -p 3.333
 	@echo $(SUCCESS)
 
-$(RS_TARGET):$(TAPA_XO) $(DEVICE_CONFIG)
+$(RS_TARGET):$(TAPA_XO) $(DEVICE_CONFIG) $(RS_SCRIPT)
 	mkdir -p $(TEMP_DIR)
 	cd $(RSPATH) && $(RSXX)-tapaopt \
     --work-dir $(TEMP_DIR) \
     --tapa-xo-path $< \
     --device-config $(DEVICE_CONFIG) \
     --floorplan-config $(AB_CONFIG) \
-	--single-reg \
     --run-impl \
     --implementation-config $(IMPL_CONFIG) \
     --connectivity-ini $(LINK_CONFIG)
 
-$(DEVICE_CONFIG):$(AB_CONFIG)
+device: $(DEVICE_CONFIG)
+
+$(DEVICE_CONFIG):$(RS_SCRIPT)
 	mkdir -p $(TEMP_DIR)
-	cd $(RSPATH) && $(RSPYTHON) $(RS_SCRIPT)
+	cd $(RSPATH) && $(RSPYTHON) $<
 
 show_groups:
 	rapidstream $(GRP_UTIL) -i $(TEMP_DIR)/passes/0-imported.json \

benchmarks/tapa_flow/orcDecoder/README.md

@@ -24,95 +24,66 @@ In this recipe, we demonstrate how to use RapidStream to optimize TAPA projects.
 We utilize TAPA to generate the `.xo` file. If you have not installed TAPA, we've already compiled the C++ source to `.xo` using TAPA. The original C++ source files are located in [design/src](design/src). The generated `.xo` file can be found at [design/generated/data_decoding.xo](design/generated/data_decoding.xo). To compile C++ to `.xo` using TAPA, we use the script [design/run_tapa.sh](design/run_tapa.sh), with the detailed commands shown below. For your convenience, we have also backed up all the generated metadata by TAPA in the [design/generated](design/generated/) directory.
 
 ```bash
-WORK_DIR=generated
-tapac \
-  --work-dir ${WORK_DIR} \
-  --top data_decoding \
-  --part-num xcu280-fsvh2892-2L-e \
-  --clock-period 3.33 \
-  -o ${WORK_DIR}/data_decoding.xo \
-  --connectivity config/link_config.ini \
-  src/data_decoder.cpp \
-  2>&1 | tee tapa.log
+mkdir -p build/run_u55c.py
+cd build/run_u55c.py && tapa compile \
+--top data_decoding \
+--part-num xcu55c-fsvh2892-2L-e \
+--clock-period 3.33 \
+-o data_decoding.xo \
+-f $< \
+2>&1 | tee tapa.log
+
+
 ```
 
-### Step 2: Use Rapidstream to Optimize `.xo` Design
 
-The RapidStream flow conducts design space exploration and generates solutions  by taking all TAPA-generated `.xo` file as the input.
-The RapidStream flow for TAPA requires the following key inputs:
 
-- **Platform**: The Vitis platform (e.g., `xilinx_u280_gen3x16_xdma_1_202211_1`).
-- **Device**: virtual device define by calling rapidstream APIs based on platform (e.g., `get_u280_vitis_device_factory`).
-- **.xo file**: The `.xo` file generated by TAPA
-- **Connectivity** (.ini): Include the configuration file for `v++` ([link_config.ini](design/config/run.py/link_config.ini)).
-- **top_module_name**: Top module name for the kernel.
-- **Clock**: All the clock and frequencies.
-- **Flatten Module**: Within a design, not all modules need to be optimized. The flatten module name is the target module rapidstream will optimize.
-
-The Python snippet below shows how we initiate rapidstream instance to set up the rapidstream environment.
-
-```Python
-from rapidstream import get_u280_vitis_device_factory, RapidStreamTAPA
-import os
-
-CURR_DIR = os.path.dirname(os.path.abspath(__file__))
-INI_PATH = f"{CURR_DIR}/design/config/link_config.ini"
-VITIS_PLATFORM = "xilinx_u280_gen3x16_xdma_1_202211_1"
-XO_PATH = f"{CURR_DIR}/design/generated/data_decoding.xo"
-kernel_name = "data_decoding"
-factory = get_u280_vitis_device_factory(VITIS_PLATFORM)
-rs = RapidStreamTAPA(f"{CURR_DIR}/build")
-rs.set_virtual_device(factory.generate_virtual_device())
-rs.add_xo_file(XO_PATH)
-rs.set_vitis_platform(VITIS_PLATFORM)
-rs.set_vitis_connectivity_config(INI_PATH)
-rs.set_top_module_name(kernel_name)
-rs.add_clock("ap_clk", 3.33)
-rs.add_flatten_targets([kernel_name])
-```
+### Step 2: Define Virtual Device
+
+In this tutorial, we use the [Alveo U55C](https://www.amd.com/en/products/accelerators/alveo/u55c/a-u55c-p00g-pq-g.html) as an example. The device is organized into six slots, each
+containing 16 clock regions of logic. In actual implementations, the available slots are reduced
+ based on the platform specifics, as some resources are reserved for shell logic.
 
-The HBM AXI port connection is described in [design/config/link_config.ini](design/config/run.py/link_config.ini).
+<img src="../../../common/img/au55c_virtual_device.jpg" width="400px" alt="AU55C Device"/>
+
+To generate a `device.json` file that details the device features, such as slot resources and
+ locations, you can either run the `run_u55c.py` script by invoking RapidStream as shown below or
+ simply enter `make device` in the terminal.
 
 ```bash
-[connectivity]
-sp=data_decoding.input_port:HBM[0:1]
-sp=data_decoding.output_port0_32b_8b:HBM[16:17]
-sp=data_decoding.output_port1_16b_8b:HBM[18:19]
-sp=data_decoding.output_port2_16b_8b:HBM[20:21]
-sp=data_decoding.output_port3_8b:HBM[22:23]
-sp=data_decoding.output_port4_Track:HBM[24:25]
+rapidstream run_u55c.py
 ```
 
-As a result, it is necessary to assign the kernel ports to the appropriate slots. The Python code below demonstrates this process. For comprehensive linking details, please refer to the [design/config/link_config.ini](design/config/run.py/link_config.ini) file.
-
- ```Python
-# Bind ports to HBM 16-31
-right_slot = "SLOT_X1Y0:SLOT_X1Y0"
-left_slot = "SLOT_X0Y0:SLOT_X0Y0"
-rs.assign_port_to_region(".*input_port.*", left_slot)
-rs.assign_port_to_region(".*output_port0_32b_8b.*", right_slot)
-rs.assign_port_to_region(".*output_port1_16b_8b.*", right_slot)
-rs.assign_port_to_region(".*output_port2_16b_8b.*", right_slot)
-rs.assign_port_to_region(".*output_port3_8b.*", right_slot)
-rs.assign_port_to_region(".*output_port4_Track.*", right_slot)
-rs.assign_port_to_region("s_axi_control_.*", left_slot)
-rs.assign_port_to_region("ap_clk", left_slot)
-rs.assign_port_to_region("ap_rst_n", left_slot)
-rs.assign_port_to_region("interrupt", left_slot)
-```
 
-For the complete detail, please refore to [./run.py](./run.py) file. Call the rapidstream by launching the command below or `make all`.
+### Step 3: Use Rapidstream to Optimize `.xo` Design
+
+The RapidStream flow conducts design space exploration and generates solutions  by taking all TAPA-generated `.xo` file as the input.
+The RapidStream flow for TAPA requires the following key inputs:
+
+- **tapa-xo-path**: The path to the tapa-generated `xo` file (digit_recognizer.xo).
+- **device-config**: The virtual device (`device.json`) generated in previous step 2 by calling rapidstream APIs based on platform.
+- **floorplan-config**: The configure file ([floorplan_config.json](design/config/run_u55c.py/floorplan_config.json)) to guide integrated Autobridge to floorplan the design.
+- **implementation-config**: The configure file ([impl_config.json](design/config/run_u55c.py/impl_config.json)) to guide Vitis to implement the design (e.g., kernek clock, vitis_platform and etc.).
+- **connectivity-ini**: The link configure file ([link_config.ini](design/config/run_u55c.py/link_config.ini)) to specify how the kernel interfaces are connected the memory controller. This is
+the same for vitis link configure file.
+
+We encapulate the rapidstream command for TAPA as `rapidstream-tapaopt` for invoking.
+You can run the command below or execute `make all` supported by our [Makefile](Makefile).
 
 ```bash
-rapidstream run.py
+rapidstream-tapaopt --work-dir build/run_u55c.py \
+                    --tapa-xo-path design/generated/data_decoding.xo \
+                    --device-config build/run_u55c.py/device.json \
+                    --floorplan-config design/config/run_u55c.py/floorplan_config.json \
+                    --implementation-config design/config/run_u55c.py/impl_config.json \
+                    --connectivity-ini design/config/run_u55c.py/link_config.ini
 ```
 
-If everything is successful, you should at least get one optimized `.xclbin` file.
-
 
+If everything is successful, you should at least get one optimized `.xclbin` file.
 
 
-### Step 3: Check the Group Module Report
+### Step 4: Check the Group Module Report
 
 
 RapidStream mandates a clear distinction between communication and computation within user designs.