feat(vck5000): check in VCK5000 DFX case

rapidstream-org · Dec 10, 2024 · d4ea943 · d4ea943
1 parent 71fcec6
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diff --git a/benchmarks/tapa_flow/knn_chipknn/k16D_float_27PEs/Makefile b/benchmarks/tapa_flow/knn_chipknn/k16D_float_27PEs/Makefile
@@ -3,24 +3,44 @@
 
 ROOT_DIR         := $(shell git rev-parse --show-toplevel)
 KERNEL_NAME      := Knn
-PLATFORM         := xilinx_u280_gen3x16_xdma_1_202211_1
+RS_SCRIPT        := $(CURDIR)/run.py
+AB_CONFIG        := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/ab_config.json
+IMPL_CONFIG      := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/impl_config.json
+LINK_CONFIG      := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/link_config.ini
+PLATFORM         := xilinx_u55c_gen3x16_xdma_3_202210_1
 GRP_UTIL         := $(ROOT_DIR)/common/util/get_group.py
-RS_SCRIPT        := run.py
 TEMP_DIR         := $(CURDIR)/build/$(notdir $(RS_SCRIPT))
-RS_TARGET        := $(TEMP_DIR)/dse/candidate_0/vitis_run_hw/$(KERNEL_NAME)_$(PLATFORM).xclbin
+RS_TARGET        := $(TEMP_DIR)/dse/solution_0/vitis_run_hw/$(KERNEL_NAME)_$(PLATFORM).xclbin
 TAPA_XO          := $(CURDIR)/design/generated/knn.xo
-PART             := xcu280-fsvh2892-2L-e
 BUILD_LOG        := $(TEMP_DIR)/build.json
 SUCCESS          := "Build Successful"
 TIMING_RPT       := impl_1_hw_bb_locked_timing_summary_routed.rpt
 SLACK_GETTER     := $(ROOT_DIR)/common/util/get_slack.py
+RSPATH           := $(CURDIR)
+RSXX             := rapidstream
+RSPYTHON         := rapidstream
+DEVICE_CONFIG    := $(TEMP_DIR)/device.json
+DEVICE_GEN       := $(CURDIR)/gen_device.py
 
 all: $(RS_TARGET)
-	$(RSXX)	$(SLACK_GETTER) -d $(TEMP_DIR) -i $(TIMING_RPT) -o $(BUILD_LOG)  -c clk_kernel_00_unbuffered_net -p 3.333
+	cd $(RSPATH) && $(RSPYTHON)	$(SLACK_GETTER) -d $(TEMP_DIR) -i $(TIMING_RPT) -o $(BUILD_LOG)  -c clk_kernel_00_unbuffered_net -p 3.333
 	@echo $(SUCCESS)
 
-$(RS_TARGET):$(TAPA_XO)
-	$(RSXX) $(RS_SCRIPT)
+$(RS_TARGET):$(TAPA_XO) $(DEVICE_CONFIG)
+	mkdir -p $(TEMP_DIR)
+	cd $(RSPATH) && $(RSXX)-tapaopt \
+    --work-dir $(TEMP_DIR) \
+    --tapa-xo-path $< \
+    --device-config $(DEVICE_CONFIG) \
+    --floorplan-config $(AB_CONFIG) \
+	--single-reg \
+    --run-impl \
+    --implementation-config $(IMPL_CONFIG) \
+    --connectivity-ini $(LINK_CONFIG)
+
+$(DEVICE_CONFIG):$(AB_CONFIG)
+	mkdir -p $(TEMP_DIR)
+	cd $(RSPATH) && $(RSPYTHON) $(RS_SCRIPT)
 
 show_groups:
 	rapidstream $(GRP_UTIL) -i $(TEMP_DIR)/passes/0-imported.json \

diff --git a/benchmarks/tapa_flow/knn_chipknn/k16D_float_27PEs/README.md b/benchmarks/tapa_flow/knn_chipknn/k16D_float_27PEs/README.md
@@ -44,7 +44,7 @@ The RapidStream flow for TAPA requires the following key inputs:
 - **Platform**: The Vitis platform (e.g., `xilinx_u280_gen3x16_xdma_1_202211_1`).
 - **Device**: virtual device define by calling rapidstream APIs based on platform (e.g., `get_u280_vitis_device_factory`).
 - **.xo file**: The `.xo` file generated by TAPA
-- **Connectivity** (.ini): Include the configuration file for `v++` ([link_config.ini](design/config/link_config.ini)).
+- **Connectivity** (.ini): Include the configuration file for `v++` ([link_config.ini](design/config/run.py/link_config.ini)).
 - **top_module_name**: Top module name for the kernel.
 - **Clock**: All the clock and frequencies.
 - **Flatten Module**: Within a design, not all modules need to be optimized. The flatten module name is the target module rapidstream will optimize.
@@ -70,7 +70,7 @@ rs.add_clock("ap_clk", 3.33)
 rs.add_flatten_targets([kernel_name])
 ```
 
-The HBM AXI port connection is described in [design/config/link_config.ini](design/config/link_config.ini).
+The HBM AXI port connection is described in [design/config/link_config.ini](design/config/run.py/link_config.ini).
 
 ```bash
 [connectivity]
@@ -105,7 +105,7 @@ sp=Knn.final_out_dist:HBM[26]
 sp=Knn.final_out_id:HBM[26]
 ```
 
-As a result, it is necessary to assign the kernel ports to the appropriate slots. The Python code below demonstrates this process. For comprehensive linking details, please refer to the [design/config/link_config.ini](design/config/link_config.ini) file.
+As a result, it is necessary to assign the kernel ports to the appropriate slots. The Python code below demonstrates this process. For comprehensive linking details, please refer to the [design/config/link_config.ini](design/config/run.py/link_config.ini) file.
 
  ```Python
 right_slot = "SLOT_X1Y0:SLOT_X1Y0"

diff --git a/benchmarks/tapa_flow/knn_chipknn/k16D_float_27PEs/design/config/link_config.ini b/benchmarks/tapa_flow/knn_chipknn/k16D_float_27PEs/design/config/link_config.ini
diff --git a/benchmarks/tapa_flow/knn_chipknn/k16D_float_27PEs/design/config/run.py/link_config.ini b/benchmarks/tapa_flow/knn_chipknn/k16D_float_27PEs/design/config/run.py/link_config.ini
@@ -1,18 +1,30 @@
 [connectivity]
-sp=Knn_1.in_0:HBM[0]
-sp=Knn_1.in_1:HBM[1]
-sp=Knn_1.in_2:HBM[2]
-sp=Knn_1.in_3:HBM[3]
-sp=Knn_1.in_4:HBM[4]
-sp=Knn_1.in_5:HBM[5]
-sp=Knn_1.in_6:HBM[6]
-sp=Knn_1.in_7:HBM[7]
-sp=Knn_1.in_8:HBM[8]
-sp=Knn_1.in_9:HBM[9]
-sp=Knn_1.in_10:HBM[10]
-sp=Knn_1.in_11:HBM[11]
-sp=Knn_1.in_12:HBM[12]
-sp=Knn_1.in_13:HBM[13]
-sp=Knn_1.in_14:HBM[14]
-sp=Knn_1.final_out_dist:HBM[14]
-sp=Knn_1.final_out_id:HBM[14]
+sp=Knn.in_0:HBM[0]
+sp=Knn.in_1:HBM[1]
+sp=Knn.in_2:HBM[2]
+sp=Knn.in_3:HBM[3]
+sp=Knn.in_4:HBM[4]
+sp=Knn.in_5:HBM[5]
+sp=Knn.in_6:HBM[6]
+sp=Knn.in_7:HBM[7]
+sp=Knn.in_8:HBM[8]
+sp=Knn.in_9:HBM[9]
+sp=Knn.in_10:HBM[10]
+sp=Knn.in_11:HBM[11]
+sp=Knn.in_12:HBM[12]
+sp=Knn.in_13:HBM[13]
+sp=Knn.in_14:HBM[14]
+sp=Knn.in_15:HBM[15]
+sp=Knn.in_16:HBM[16]
+sp=Knn.in_17:HBM[17]
+sp=Knn.in_18:HBM[18]
+sp=Knn.in_19:HBM[19]
+sp=Knn.in_20:HBM[20]
+sp=Knn.in_21:HBM[21]
+sp=Knn.in_22:HBM[22]
+sp=Knn.in_23:HBM[23]
+sp=Knn.in_24:HBM[24]
+sp=Knn.in_25:HBM[25]
+sp=Knn.in_26:HBM[26]
+sp=Knn.final_out_dist:HBM[26]
+sp=Knn.final_out_id:HBM[26]
diff --git a/benchmarks/tapa_flow/knn_chipknn/k16D_float_27PEs/design/generated/knn.xo b/benchmarks/tapa_flow/knn_chipknn/k16D_float_27PEs/design/generated/knn.xo
diff --git a/benchmarks/tapa_flow/knn_chipknn/k16D_float_27PEs/run.py b/benchmarks/tapa_flow/knn_chipknn/k16D_float_27PEs/run.py
@@ -3,88 +3,26 @@
 The contributor(s) of this file has/have agreed to the RapidStream Contributor License Agreement.
 """
 
-from rapidstream import get_u280_vitis_device_factory, RapidStreamTAPA
+from pathlib import Path
+from rapidstream import get_u55c_vitis_device_factory
 import os
 
 CURR_DIR = os.path.dirname(os.path.abspath(__file__))
-INI_PATH = f"{CURR_DIR}/design/config/link_config.ini"
-VITIS_PLATFORM = "xilinx_u280_gen3x16_xdma_1_202211_1"
-XO_PATH = f"{CURR_DIR}/design/generated/knn.xo"
-kernel_name = "Knn"
-
-factory = get_u280_vitis_device_factory(VITIS_PLATFORM)
+CURR_FILE = os.path.basename(__file__)
+VITIS_PLATFORM = (
+    "xilinx_u55c_gen3x16_xdma_3_202210_1"  # "xilinx_u280_gen3x16_xdma_1_202211_1"
+)
 
-# Reserve resource for the HBM Memory Sub-System.
-# The HMSS is not part of the user kernel so the partition optimization process
-# is unaware of its existence. We need to manually reserve resources for it.
-# For 512-bit HBM channels, each HBM channel uses approximately the following resources:
-# AREA_PER_HBM_CHANNEL = {
-#     "LUT": 5000,
-#     "FF": 6500,
-#     "BRAM": 0,
-#     "URAM": 0,
-#     "DSP": 0,
-# }
-factory.reduce_slot_area(1, 0, lut=5000 * 16, ff=6500 * 16)
-factory.reduce_slot_area(0, 0, lut=5000 * 13, ff=6500 * 13)
+factory = get_u55c_vitis_device_factory(VITIS_PLATFORM)
 
-# For this U280 platform, the right most DSP column on the boundary between
-# dynamic/static region is not usable. So we need to adjust the DSP count
-# to reflect the actual available DSPs.
-print("Reducing DSP of (1, 1) to make it less congested")
+factory.reduce_slot_area(1, 0, lut=50000, ff=60000)
+factory.reduce_slot_area(0, 0, lut=50000, ff=60000)
 factory.reduce_slot_area(1, 1, dsp=100)
 
-rs = RapidStreamTAPA(f"{CURR_DIR}/build/{os.path.basename(__file__)}")
-
-rs.set_virtual_device(factory.generate_virtual_device())
-rs.add_xo_file(XO_PATH)
-rs.set_vitis_platform(VITIS_PLATFORM)
-rs.set_vitis_connectivity_config(INI_PATH)
-
-rs.set_top_module_name(kernel_name)
-rs.add_clock("ap_clk", 3.33)
-
-rs.add_flatten_targets([kernel_name])
+factory.generate_virtual_device(Path(f"{CURR_DIR}/build/{CURR_FILE}/device.json"))
 
-# Bind ports to HBM 16-31
-right_slot = "SLOT_X1Y0:SLOT_X1Y0"
-left_slot = "SLOT_X0Y0:SLOT_X0Y0"
-# The config file binds the following argument to HBM 0 - 15
-# sp=Knn_1.in_0:HBM[0]
-# sp=Knn_1.in_1:HBM[1]
-# sp=Knn_1.in_2:HBM[2]
-# sp=Knn_1.in_3:HBM[3]
-# sp=Knn_1.in_4:HBM[4]
-# sp=Knn_1.in_5:HBM[5]
-# sp=Knn_1.in_6:HBM[6]
-# sp=Knn_1.in_7:HBM[7]
-# sp=Knn_1.in_8:HBM[8]
-# sp=Knn_1.in_9:HBM[9]
-# sp=Knn_1.in_10:HBM[10]
-# sp=Knn_1.in_11:HBM[11]
-# sp=Knn_1.in_12:HBM[12]
-# sp=Knn_1.in_13:HBM[13]
-# sp=Knn_1.in_14:HBM[14]
-# sp=Knn_1.final_out_dist:HBM[14]
-# sp=Knn_1.final_out_id:HBM[14]
 
-rs.assign_port_to_region(".*in_.*", left_slot)
-rs.assign_port_to_region(".*final_out.*", left_slot)
-
-# Constrain the remaining control ports.
-# All ports must be constrained to a specific slot:
-rs.assign_port_to_region("s_axi_control_.*", left_slot)
-rs.assign_port_to_region("ap_clk", left_slot)
-rs.assign_port_to_region("ap_rst_n", left_slot)
-rs.assign_port_to_region("interrupt", left_slot)
-
-# Xustomize the placement strategy:
-rs.set_placement_strategy("EarlyBlockPlacement")
-
-# Allow two parallel Vitis implementation
-rs.run_dse(
-    max_workers=2,
-    max_dse_limit=0.85,
-    min_dse_limit=0.75,
-    partition_strategy="flat",
-)
+# ab_config = FloorplanConfig(
+#    port_pre_assignments={".*": "SLOT_X0Y0:SLOT_X0Y0"},
+# )
+# ab_config.save_to_file("test.json")
diff --git a/benchmarks/vivado_flow/vck5000_dfx/Makefile b/benchmarks/vivado_flow/vck5000_dfx/Makefile
@@ -0,0 +1,39 @@
+# Copyright (c) 2024 RapidStream Design Automation, Inc. and contributors.  All rights reserved.
+# The contributor(s) of this file has/have agreed to the RapidStream Contributor License Agreement.
+
+
+TEMP_DIR := $(CURDIR)/build
+VPP      := vivado -mode batch -source
+OVERLAY  := $(TEMP_DIR)/overlay.dcp
+OOC      := $(TEMP_DIR)/vadd_bw.dcp
+PROVERLAY:= $(TEMP_DIR)/pr_overlay.dcp
+m=$(shell date)
+
+all:$(PROVERLAY)
+
+$(PROVERLAY): $(CURDIR)/tcl/impl.tcl $(OVERLAY) $(OOC)
+	mkdir -p $(TEMP_DIR)
+	cd $(TEMP_DIR) && $(VPP) $<
+
+overlay: $(OVERLAY)
+
+$(OVERLAY): $(CURDIR)/tcl/prj_gen.tcl
+	mkdir -p $(TEMP_DIR)
+	cd $(TEMP_DIR) && $(VPP) $<
+
+ooc: $(OOC)
+
+$(OOC): $(CURDIR)/tcl/ooc_syn.tcl
+	mkdir -p $(TEMP_DIR)
+	cd $(TEMP_DIR) && $(VPP) $<
+
+proverlay:$(PROVERLAY)
+
+
+git:
+	git add .
+	git commit -m "$(m)"
+	git push origin main
+
+clean:
+	rm -rf $(TEMP_DIR)
diff --git a/benchmarks/vivado_flow/vck5000_dfx/README.md b/benchmarks/vivado_flow/vck5000_dfx/README.md
@@ -0,0 +1,11 @@
+<!--
+Copyright (c) 2024 RapidStream Design Automation, Inc. and contributors.  All rights reserved.
+The contributor(s) of this file has/have agreed to the RapidStream Contributor License Agreement.
+-->
+
+# How to make VCK5000 Overlay
+
+1. Copy vck5000 to <your Vivado installation>/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx
+2. make all.
+3. Find the proverlay.dcp in build directory.
+4. make your design have the same interface as ./v/vadd_bandwidth28r28w_placeholder.