GitHub - sjn4048/LCDF_Project_Verilog_Game: A Verilog game for LCDF @ ZJU

Branches Tags

Name		Name	Last commit message	Last commit date
Latest commit History 6 Commits
_xmsgs		_xmsgs
ipcore_dir		ipcore_dir
iseconfig		iseconfig
.gitignore		.gitignore
Anti_jitter.sym		Anti_jitter.sym
Display.sch		Display.sch
Display.sym		Display.sym
ExMUX_sch.sch		ExMUX_sch.sch
ExMUX_sch.sym		ExMUX_sch.sym
FINAL_PROJECT.gise		FINAL_PROJECT.gise
FINAL_PROJECT.xise		FINAL_PROJECT.xise
Framework_ucf.ucf		Framework_ucf.ucf
GPIO.sym		GPIO.sym
GPIO.v		GPIO.v
Game_ucf.ucf		Game_ucf.ucf
Hex27SegDecoder_sch.sch		Hex27SegDecoder_sch.sch
Hex27SegDecoder_sch.sym		Hex27SegDecoder_sch.sym
Hex2Seg.v		Hex2Seg.v
HexTo8SEG.sym		HexTo8SEG.sym
HexTo8SEG.v		HexTo8SEG.v
InputT32.sym		InputT32.sym
LED_P2S.v		LED_P2S.v
MUX2T1_64.sym		MUX2T1_64.sym
MUX2T1_64.v		MUX2T1_64.v
MUX2T1_8.sym		MUX2T1_8.sym
MUX2T1_8.v		MUX2T1_8.v
MUX441_sch.sch		MUX441_sch.sch
MUX441_sch.sym		MUX441_sch.sym
MUX4T1_4.sym		MUX4T1_4.sym
MUX8T1_32.sch		MUX8T1_32.sch
MUX8T1_32.sym		MUX8T1_32.sym
MUX8T1_8.sym		MUX8T1_8.sym
Multi_8CH32.sym		Multi_8CH32.sym
Multi_8CH32.v		Multi_8CH32.v
P2S.sym		P2S.sym
P2S.v		P2S.v
PIO.sym		PIO.sym
PIO.v		PIO.v
Press_Logic.sym		Press_Logic.sym
Press_Logic.v		Press_Logic.v
Press_Logic_test.v		Press_Logic_test.v
SAnti_Jitter_test.v		SAnti_Jitter_test.v
SAnti_jitter.sym		SAnti_jitter.sym
SAnti_jitter.v		SAnti_jitter.v
SEnter_2_32.sym		SEnter_2_32.sym
SEnter_2_32.v		SEnter_2_32.v
SSeg_map.sym		SSeg_map.sym
SSeg_map.v		SSeg_map.v
ScanSync_8.sch		ScanSync_8.sch
ScanSync_8.sym		ScanSync_8.sym
Seg7_Dev.sch		Seg7_Dev.sch
Seg7_Dev.sym		Seg7_Dev.sym
Seg7_Dev16.sym		Seg7_Dev16.sym
Seg_Decoder.v		Seg_Decoder.v
Seg_map.sym		Seg_map.sym
Seg_map.v		Seg_map.v
Seven_Seg_Display.sym		Seven_Seg_Display.sym
Seven_Seg_Display.v		Seven_Seg_Display.v
Seven_Seg_Display_test.v		Seven_Seg_Display_test.v
VGA.sym		VGA.sym
VGA.v		VGA.v
VGA_Display.sym		VGA_Display.sym
VGA_Display.v		VGA_Display.v
VGA_Display_Test.v		VGA_Display_Test.v
clkdiv.sym		clkdiv.sym
clkdiv.v		clkdiv.v
framework_sch.sch		framework_sch.sch
framework_sch.sym		framework_sch.sym
framework_test.v		framework_test.v
logic.jpg		logic.jpg
lose.bmp		lose.bmp
lose.coe		lose.coe
random.sym		random.sym
random.v		random.v
random_test.v		random_test.v