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xy-241 · Dec 21, 2023 · bf6379f · bf6379f
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diff --git a/...truction Set Architecture (ISA)/Instruction Encoding/Expanding Opcode Scheme.md b/...truction Set Architecture (ISA)/Instruction Encoding/Expanding Opcode Scheme.md
diff --git a/...tion Set Architecture (ISA)/Instruction Execution/Multi-Cycle Implementation.md b/...tion Set Architecture (ISA)/Instruction Execution/Multi-Cycle Implementation.md
diff --git a/content/Computer Organisation/Instruction Set Architecture (ISA)/Instruction.md b/content/Computer Organisation/Instruction Set Architecture (ISA)/Instruction.md
@@ -6,21 +6,19 @@ Author Profile:
 tags:
   - computer_organisation
 Creation Date: 2023-09-28T09:59:05+08:00
-Last Date: 2023-12-18T16:54:03+08:00
+Last Date: 2023-12-21T15:10:57+08:00
 References: 
 ---
 ## Abstract
 ---
 - Also known as *Machine Codes*
-- [[Bit String]] stored in the [[Main Memory]]
+- [[Bit String]]
 - Passed to CPU to get translated to carry out [[Operation]]
 - Doesn't specify which [[CPU Datapath]] does what, just specify what outputs are expected with a given input
 - The instruction lifecycle can be broken down into [[Pipeline Stages]]
-- Made up of 2 parts - [[#Opcode]] & [[#Parameter]]
 - 2 forms - [[#Fixed-length]] & [[#Variable-length]]
 
-
-## Terminologies
+## 2 Parts
 ---
 ### Opcode
 - Config for [[Control Unit#Control Signal]]
@@ -29,6 +27,10 @@ References:
 - [[Register]] Address
 - [[Memory Address]]
 - Immediate Value
+
+
+## Terminologies
+---
 ### Branch
 - An [[Instruction]] that causes [[Process]] to jump to a different location in the codes
 
@@ -40,4 +42,7 @@ References:
 
 ### Single Instruction Multiple Data
 - This allows one [[Instruction]] to operate on multiple data at once and have multiple outputs essentially
-- This can reduce the number of instructions in a program significantly, and have more data processed without the involvement of the inefficient [[Main Memory]]
+- This can reduce the number of instructions in a program significantly, and have more data processed without the involvement of the inefficient [[Main Memory]]
+
+### Expanding Opcode Scheme
+- The [[#Opcode]] in an [[Instruction]] can be *extended* to accommodate additional instructions in the future without changing the basic format of the instruction set
diff --git a/...Organisation/Instruction Set Architecture (ISA)/RISCV/RISCV Kernel Deep Dive.md b/...Organisation/Instruction Set Architecture (ISA)/RISCV/RISCV Kernel Deep Dive.md
@@ -6,17 +6,17 @@ Author Profile:
 tags:
   - computer_organisation
 Creation Date: 2023-12-01T21:55:00
-Last Date: 2023-12-01T22:03:51+08:00
-References:
+Last Date: 2023-12-21T15:16:36+08:00
+References: 
 ---
 ## Abstract
 ---
-- The kernel we are playing is [xv6-riscv](https://github.com/mit-pdos/xv6-riscv)
+- The [[Kernel]] we are playing is [xv6-riscv](https://github.com/mit-pdos/xv6-riscv)
 
 
-## Compilation of the [[Kernel]]
+## Compilation of the Kernel
 ---
-```bash
+```bash /128M/ /2/
 docker run --rm -v $(pwd):/project -it --platform linux/amd64 yuxinyang/rv-tool-chain:latest make
 docker run --rm -v $(pwd):/project -it --platform linux/amd64 yuxinyang/rv-tool-chain:latest make fs.img