Skip to content

2....b)Software:⑤Vivado Project Generation

Jump to bottom
Tingyuan LIANG edited this page Aug 30, 2018 · 8 revisions

The generation of Vivado project is actually based on a Tcl template. To replace some elements in the template properly can set up interconnection between HLS modules generated by Hi-DMM.

APPIPNAME is the name of the top function.

HIDMMAPPPORTNAM is the name of the particular port for Hi-DMM communication.

HIDMMALLOCATORNAME is the name of the corresponding allocator, connected to the port.

An example of template used by Hi-DMM is shown below.

connect_bd_net [get_bd_pins APPIPNAME/HIDMMAPPPORTNAME_cmd] [get_bd_pins HIDMMALLOCATORNAME/alloc_cmd]
connect_bd_net [get_bd_pins APPIPNAME/HIDMMAPPPORTNAME_free_target] [get_bd_pins HIDMMALLOCATORNAME/alloc_free_target]
connect_bd_net [get_bd_pins APPIPNAME/HIDMMAPPPORTNAME_size] [get_bd_pins HIDMMALLOCATORNAME/alloc_size]
connect_bd_net [get_bd_pins APPIPNAME/HIDMMAPPPORTNAME_size_ap_vld] [get_bd_pins HIDMMALLOCATORNAME/alloc_size_ap_vld]
connect_bd_net [get_bd_pins HIDMMALLOCATORNAME/alloc_free_target_ap_vld] [get_bd_pins APPIPNAME/HIDMMAPPPORTNAME_free_target_ap_vld]
connect_bd_net [get_bd_pins HIDMMALLOCATORNAME/alloc_addr_ap_ack] [get_bd_pins APPIPNAME/HIDMMAPPPORTNAME_addr_ap_ack]
connect_bd_net [get_bd_pins APPIPNAME/HIDMMAPPPORTNAME_cmd_ap_vld] [get_bd_pins HIDMMALLOCATORNAME/alloc_cmd_ap_vld]
connect_bd_net [get_bd_pins HIDMMALLOCATORNAME/alloc_size_ap_ack] [get_bd_pins APPIPNAME/HIDMMAPPPORTNAME_size_ap_ack]
connect_bd_net [get_bd_pins HIDMMALLOCATORNAME/alloc_free_target_ap_ack] [get_bd_pins APPIPNAME/HIDMMAPPPORTNAME_free_target_ap_ack]
connect_bd_net [get_bd_pins HIDMMALLOCATORNAME/alloc_addr_ap_vld] [get_bd_pins APPIPNAME/HIDMMAPPPORTNAME_addr_ap_vld]
connect_bd_net [get_bd_pins APPIPNAME/HIDMMAPPPORTNAME_cmd_ap_ack] [get_bd_pins HIDMMALLOCATORNAME/alloc_cmd_ap_ack]
connect_bd_net [get_bd_pins HIDMMALLOCATORNAME/alloc_addr] [get_bd_pins APPIPNAME/HIDMMAPPPORTNAME_addr]

An example of the targe project, which can be synthesized and implemented in Vivado, is shown below. (Note that clock signals and related clock circuits are removed from the example to make the interconnection between modules clear.)

Clone this wiki locally