Dnb mult deq #32
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Dnb mult deq #32
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erlingrj
commented
Mar 23, 2020
erlingrj
commented
- Also use SRAM FIFOs for DNB
- Add support for multiple dequeue of DLQ/CRQ
… into DNB-dev-merge
… into DNB-dev-merge
… into DNB-dev-merge
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@davidmetz In this PR there are some changes to the Unified Issue Unit, you might wanna check those out |
davidmetz
reviewed
Mar 23, 2020
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| for (w <- 0 until enqWidth) | ||
| { | ||
| io.enq_uops(w).ready := !full |
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not sure if this works with out of order deq
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as soon as one valid is false it's not full
but that could be because head+1 was dequeued but not head
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I think it would work because:
- full = at least 1 valid per "row". If head+1 is dequeued and not head we would still have at least one valid in that row.
- heads always belong to the same row. if head+1 is dequeued we can get (head, head+2) as heads but it will never run ahead to a new row.
- This means that the head row will count as full even when head+1 etc are dequeued
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| // Pass out the head | ||
| // Init all outputs to invalids | ||
| // A little hacking to assign a possible wider set of FIFOs to a narrower set of deq ports |
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this seems to already kind of compact
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