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Dnb mult deq #32

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Dnb mult deq #32

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2e82a6a
merged in sram based dis fifos
erlingrj Mar 18, 2020
b5db1a3
merged in sram based dis fifos
erlingrj Mar 18, 2020
95b1324
Merge branch 'DNB-dev-merge' of https://github.com/EECS-NTNU/riscv-bo…
erlingrj Mar 18, 2020
1fb9639
Merge branch 'DNB-dev-merge' of https://github.com/EECS-NTNU/riscv-bo…
erlingrj Mar 18, 2020
2b64448
Merge branch 'DNB-dev-merge' of https://github.com/EECS-NTNU/riscv-bo…
erlingrj Mar 18, 2020
a1af78d
test
erlingrj Mar 18, 2020
2608e5d
Do branch resolution update on enq->head bypasses also
erlingrj Mar 19, 2020
4c401b2
[dis-q] Missing closing bracket
erlingrj Mar 19, 2020
f7b1b59
[dis-q] corred br_mask update for bypassed heads
erlingrj Mar 19, 2020
7771eeb
[dis-q] corred br_mask update for bypassed heads
erlingrj Mar 19, 2020
3c413b4
Start supporting multiple dequeues of CRQ and DLQ
erlingrj Mar 19, 2020
8bb41a2
[dnb-issue] Support SRAM based FIFO and multiple deq
erlingrj Mar 19, 2020
855b5ce
[params] Update require
erlingrj Mar 20, 2020
3e98bff
[dnb-iss] connect mismatch
erlingrj Mar 20, 2020
87e0a0d
[dnb-iss] fix typo
erlingrj Mar 20, 2020
bb1cc57
[dnb-iss] fix dlq issue bug and add asserts
erlingrj Mar 20, 2020
3a4ca90
[dnb-iss] assert typo
erlingrj Mar 20, 2020
d0782d4
[dnb-iss] remove mistaken assert
erlingrj Mar 20, 2020
26e6ba1
[dis-q] specfy lscMode for in-order deq and change to SRAM for DNB
erlingrj Mar 20, 2020
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6 changes: 4 additions & 2 deletions src/main/scala/common/config-mixins.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -217,15 +217,17 @@ class WithDnbBooms extends Config((site, here, up) => {
usingFPU = true,
dnbParams = Some(DnbParams(
numCrqEntries = 8,
numDlqEntries = 8
numDlqEntries = 8,
crqDispatches = 2,
dlqDispatches = 2,
)),
ibdaParams = Some(IbdaParams(
ibdaTagType = IBDA_TAG_FULL_PC,
rdtIstMarkWidth = 1
)),
busyLookupParams = Some(BusyLookupParams(
lookupAtRename = true,
lookupAtDisWidth = 1
lookupAtDisWidth = 2
))

),
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5 changes: 4 additions & 1 deletion src/main/scala/common/parameters.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -111,7 +111,7 @@ case class BoomCoreParams(
require(busyLookupParams.get.lookupAtDisWidth == loadSliceCore.get.dispatches())
}
if (dnbMode) {
require(busyLookupParams.get.lookupAtDisWidth == 1)
require(busyLookupParams.get.lookupAtDisWidth == dnbParams.get.dlqDispatches)
}
}

Expand Down Expand Up @@ -329,7 +329,10 @@ case class DnbParams(
numCrqEntries: Int = 8,
numDlqEntries: Int = 8,
dlqRobUrgentDist: Int = 2,
crqDispatches: Int = 1,
dlqDispatches: Int = 1
){
def dispatches(): Int = crqDispatches + dlqDispatches
}

// Case class for LoadSliceCore parameters.
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