A versatile project manager system for digital hardware design projects, supporting simulation, synthesis, and verification workflows for ASIC and FPGA development using SystemVerilog.
This Makefile automates common tasks in ASIC and FPGA design projects using SystemVerilog. It handles simulation with Icarus Verilog, synthesis with Yosys, and RTL visualization. The Makefile manages project directories, supports external module imports, and includes targets for linting with Verilator. It's designed to work with multiple source files and testbenches, providing a consistent workflow for digital design projects.
Future goals:
- Critical Path Analysis
- Formal Verification Analysis
- Power Analysis
- Code Coverage Analysis
- Generate binaries for Lattice iCE40