Take Ethernet PHY out of reset so default clock is 125 Mhz #77
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| @@ -97,6 +97,9 @@ | |||
| Subsignal("cke", Pins("D2"), IOStandard("SSTL18_II")), | |||
| Subsignal("odt", Pins("J6"), IOStandard("SSTL18_II")), | |||
| ), | |||
| # Ethernet phy reset (clk125 is 25 Mhz instead of 125 Mhz if reset is active) | |||
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Can you add a link to the documentation about this?
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Thanks! You were probably the first to test the target since i just prepared it and was planning to test it in the next days. |
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Thanks Florent! When you get around to the Pano perhaps you can add DDR support? I'm struggling with timvideos/litex-buildenv#444, I'm trying to merge DDR support from into litex-boards to see if the problem has been fixed recently, but I'm in way over my head with DDR. |
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@skiphansen: the current target is minimal because i wanted to work on that and refactor/simplify the S6DDRPHY at the same time (enjoy-digital/litedram#182). I should be able to work on it in the next days (but i'm not sure which revision of the board i have, i'll have to check). |
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@enjoy-digital: Great, if you don't have a Rev C (or Rev B) I'd be more than happy to help you test, just let me know. |
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@skiphansen: i just did a test on hardware and i have a Rev C, so i should be able to help you getting the DDR working on Rev C. |
Without this change the terminal baud rate is 23,941 (measured by a scope) since the default clock is 25 Mhz instead of the expected 125 Mhz.
The master clock on the Pano comes from the Ethernet PHY which is normally 125Mhz, but it is 25 Mhz while the PHY is in reset. The active low reset pin is driven by FPGA pin R11.
See https://github.com/tomverbeure/panologic-g2#fpga-external-clocking-architecture