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Take Ethernet PHY out of reset so default clock is 125 Mhz #77

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May 26, 2020
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Take Ethernet PHY out of reset so default clock is 125 Mhz #77

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1ab4656
Take Ethernet PHY out of reset so default clock is 125 Mhz (and baud …
skiphansen May 25, 2020
0648c04
Updated comment, added link to clocking documentation.
skiphansen May 25, 2020
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4 changes: 4 additions & 0 deletions litex_boards/platforms/pano_logic_g2.py
100644 → 100755
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Original file line number Diff line number Diff line change
Expand Up @@ -97,6 +97,10 @@
Subsignal("cke", Pins("D2"), IOStandard("SSTL18_II")),
Subsignal("odt", Pins("J6"), IOStandard("SSTL18_II")),
),
# Ethernet phy reset (clk125 is 25 Mhz instead of 125 Mhz if reset is active)
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Can you add a link to the documentation about this?

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Done.

# See https://github.com/tomverbeure/panologic-g2#fpga-external-clocking-architecture
("gmii_rst_n", 0, Pins("R11"), IOStandard("LVCMOS33")),

]

# Platform -----------------------------------------------------------------------------------------
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6 changes: 6 additions & 0 deletions litex_boards/targets/pano_logic_g2.py
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Expand Up @@ -46,6 +46,12 @@ def __init__(self, sys_clk_freq=int(50e6), **kwargs):
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")

# Take Ethernet Phy out of reset for SYSCLK of 125 Mhz
gmii_rst_n = platform.request("gmii_rst_n")
self.comb += [
gmii_rst_n.eq(1)
]

# Build --------------------------------------------------------------------------------------------

def main():
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