feat(vck5000 AIE): check in AIE VecAdd benchmark

rapidstream-org · Dec 10, 2024 · 9deeeb2 · 9deeeb2
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diff --git a/README.md b/README.md
@@ -30,7 +30,7 @@ git clone https://github.com/rapidstream-org/rapidstream-cookbook.git
 cd rapidstream-cookbook
 ```
 
-You must have RapidStream installed, a valid RapidStream license, and a valid Vivado Design Suite license to download or run the cookbooks. If you are an academic researcher or would like to contribute to this cookbook, please contact us at https://rapidstream-da.com/ for a free RapidStream license.
+You must have RapidStream installed from [here](https://tapa.readthedocs.io/en/main/user/installation.html) with a valid RapidStream license, and a valid Vivado Design Suite license to download or run the cookbooks. If you are an academic researcher or would like to contribute to this cookbook, please contact us at https://rapidstream-da.com/ for a free RapidStream license.
 
 We recommend using Vivado version 2023.2 or later. Source the Vivado settings script before running the RapidStream Python scripts. For example, to source the Vivado settings script, run the following command:
 
@@ -39,10 +39,11 @@ We recommend using Vivado version 2023.2 or later. Source the Vivado settings sc
 source <Vivado_installation_path>/Vivado/2023.2/settings64.sh
 ```
 
-All RapidStream Python script recipes (`*.py`) in this cookbook should be executed using the `rapidstream` command. For example, to run `getting_started/mixed_sources/run.py`, use the following command:
+We've created a `Makefile` for each recipe in this repository to help you get started quickly. Simply navigate to the specific example directory and run `make` to compile.
 
 ```bash
-rapidstream getting_started/mixed_sources/run.py
+cd getting_started/mixed_sources
+make
 ```
 
 The default branch always matches the latest RapidStream release. Please update your software before using the recipes.
@@ -62,6 +63,9 @@ Recipes
             <td><a href="./getting_started/vitis_source">AMD Vitis Design</a></td>
             <td><a href="./getting_started/mixed_sources">Mixed Sources Design</a></td>
         </tr>
+        <tr>
+            <td><a href="./getting_started/tapa_source">Rapidstream TAPA Design</a></td>
+        </tr>
         <tr><td colspan="3"><strong>Custom Devices</strong></td></tr>
         <tr>
             <td><a href="./getting_started/device_factory_vitis_platform">Custom Vitis Platforms</a></td>
@@ -71,6 +75,78 @@ Recipes
 </table>
 
 
+<table border="0" width="100%">
+    <tbody>
+        <tr><td colspan="5"  align="center"><h2><a href="./benchmarks/tapa_flow/">TAPA Flow Benchmarks</a></h2></td></tr>
+        <tr><td colspan="5">
+            Discover how RapidStream flow streamlines FPGA acceleration design of state-of-the-art architectures, enabling you to achieve optimal performance for performance-critical systems.
+        </td></tr>
+        <tr><td colspan="5"><strong>Scientific Computation</strong></td></tr>
+        <tr>
+            <td ><strong>Design</strong></td>
+            <td><strong>Developer</strong></td>
+            <td><strong>Platforms</strong></td>
+            <td><strong>Sources</strong></td>
+            <td><strong>Purpose</strong></td>
+        </tr>
+            <td><a href="benchmarks/tapa_flow/serpens">Serpens</a></td>
+            <td><a href="https://dl.acm.org/doi/abs/10.1145/3489517.3530420">Song <i>et al.</i><br/>(FPGA '22)</a></td>
+            <td>Vitis U55C XDMA</td>
+            <td>TAPA HLS</td>
+            <td>Accelerator for general-purpose sparse-matrix dense-matrix multiplication.</td>
+        </tr>
+        </tr>
+            <td><a href="benchmarks/tapa_flow/sextans">Sextans</a></td>
+            <td><a href="https://dl.acm.org/doi/abs/10.1145/3490422.3502357">Song <i>et al.</i><br/>(FPGA '22)</a></td>
+            <td>Vitis U55C XDMA</td>
+            <td>TAPA HLS</td>
+            <td>Accelerator for general-purpose sparse-matrix dense-matrix multiplication.</td>
+        </tr>
+        </tr>
+            <td><a href="benchmarks/tapa_flow/callipepla">Callipepla</a></td>
+            <td><a href="https://dl.acm.org/doi/abs/10.1145/3543622.3573182">Song <i>et al.</i><br/>(FPGA '22)</a></td>
+            <td>Vitis U55C XDMA</td>
+            <td>TAPA HLS</td>
+            <td>Accelerator for general-purpose sparse-matrix dense-matrix multiplication.</td>
+        </tr>
+        <tr>
+            <td><a href="benchmarks/tapa_flow/digit_recognizer">KNN Digit Recognition</a></td>
+            <td><a href="https://github.com/icgrp/hipr">Xiao <i>et al.</i><br/>(FPL '22)</a></td>
+            <td>Vitis U55C XDMA</td>
+            <td>TAPA HLS</td>
+            <td>K-Nearest Neighbours for Digit Recognition.</td>
+        </tr>
+        </tr>
+            <td><a href="benchmarks/tapa_flow/bloomFilter">Bloom Filter</a></td>
+            <td><a href="https://www.sfu.ca/~zhenman/">Simon Fraser University</a></td>
+            <td>Vitis U55C XDMA</td>
+            <td>TAPA HLS</td>
+            <td>Accelerator for Bloom Filter.</td>
+        </tr>
+        </tr>
+            <td><a href="benchmarks/tapa_flow/stencil_sasa">Stencil Application</a></td>
+            <td><a href="https://www.sfu.ca/~zhenman/">Simon Fraser University</a></td>
+            <td>Vitis U55C XDMA</td>
+            <td>TAPA HLS</td>
+            <td>Accelerator for Stencil Application.</td>
+        </tr>
+        </tr>
+            <td><a href="benchmarks/tapa_flow/knn_chipknn">KNN</a></td>
+            <td><a href="https://www.sfu.ca/~zhenman/">Simon Fraser University</a></td>
+            <td>Vitis U55C XDMA</td>
+            <td>TAPA HLS</td>
+            <td>Accelerator for K-Nearest-Neighbor.</td>
+        </tr>
+        </tr>
+            <td><a href="benchmarks/tapa_flow/orcDecoder">ORC Decoder</a></td>
+            <td><a href="https://www.sfu.ca/~zhenman/">Simon Fraser University</a></td>
+            <td>Vitis U55C XDMA</td>
+            <td>TAPA HLS</td>
+            <td>Accelerator for ORC Decoder.</td>
+        </tr>
+    </tbody>
+</table>
+
 
 <table border="0" width="100%">
     <tbody>
@@ -169,85 +245,6 @@ Recipes
 </table>
 
 
-<table border="0" width="100%">
-    <tbody>
-        <tr><td colspan="5"  align="center"><h2><a href="./benchmarks/tapa_flow/">TAPA Flow Benchmarks</a></h2></td></tr>
-        <tr><td colspan="5">
-            Discover how RapidStream flow streamlines FPGA acceleration design of state-of-the-art architectures, enabling you to achieve optimal performance for performance-critical systems.
-        </td></tr>
-        <tr><td colspan="5"><strong>Scientific Computation</strong></td></tr>
-        <tr>
-            <td ><strong>Design</strong></td>
-            <td><strong>Developer</strong></td>
-            <td><strong>Platforms</strong></td>
-            <td><strong>Sources</strong></td>
-            <td><strong>Purpose</strong></td>
-        </tr>
-            <td><a href="benchmarks/tapa_flow/serpens">Serpens</a></td>
-            <td><a href="https://dl.acm.org/doi/abs/10.1145/3489517.3530420">Song <i>et al.</i><br/>(FPGA '22)</a></td>
-            <td>Vitis U280 XDMA</td>
-            <td>TAPA HLS</td>
-            <td>Accelerator for general-purpose sparse-matrix dense-matrix multiplication.</td>
-        </tr>
-        </tr>
-            <td><a href="benchmarks/tapa_flow/sextans">Sextans</a></td>
-            <td><a href="https://dl.acm.org/doi/abs/10.1145/3490422.3502357">Song <i>et al.</i><br/>(FPGA '22)</a></td>
-            <td>Vitis U250 XDMA</td>
-            <td>TAPA HLS</td>
-            <td>Accelerator for general-purpose sparse-matrix dense-matrix multiplication.</td>
-        </tr>
-        </tr>
-            <td><a href="benchmarks/tapa_flow/callipepla">Callipepla</a></td>
-            <td><a href="https://dl.acm.org/doi/abs/10.1145/3543622.3573182">Song <i>et al.</i><br/>(FPGA '22)</a></td>
-            <td>Vitis U280 XDMA</td>
-            <td>TAPA HLS</td>
-            <td>Accelerator for general-purpose sparse-matrix dense-matrix multiplication.</td>
-        </tr>
-        <tr>
-            <td><a href="benchmarks/tapa_flow/digit_recognizer">KNN Digit Recognition</a></td>
-            <td><a href="https://github.com/icgrp/hipr">Xiao <i>et al.</i><br/>(FPL '22)</a></td>
-            <td>Vitis U280 XDMA</td>
-            <td>TAPA HLS</td>
-            <td>K-Nearest Neighbours for Digit Recognition.</td>
-        </tr>
-        </tr>
-            <td><a href="benchmarks/tapa_flow/bloomFilter">Bloom Filter</a></td>
-            <td><a href="https://www.sfu.ca/~zhenman/">Simon Fraser University</a></td>
-            <td>Vitis U280 XDMA</td>
-            <td>TAPA HLS</td>
-            <td>Accelerator for Bloom Filter.</td>
-        </tr>
-        </tr>
-            <td><a href="benchmarks/tapa_flow/stencil_sasa">Stencil Application</a></td>
-            <td><a href="https://www.sfu.ca/~zhenman/">Simon Fraser University</a></td>
-            <td>Vitis U280 XDMA</td>
-            <td>TAPA HLS</td>
-            <td>Accelerator for Stencil Application.</td>
-        </tr>
-        </tr>
-            <td><a href="benchmarks/tapa_flow/knn_chipknn">KNN</a></td>
-            <td><a href="https://www.sfu.ca/~zhenman/">Simon Fraser University</a></td>
-            <td>Vitis U280 XDMA</td>
-            <td>TAPA HLS</td>
-            <td>Accelerator for K-Nearest-Neighbor.</td>
-        </tr>
-        </tr>
-            <td><a href="benchmarks/tapa_flow/orcDecoder">ORC Decoder</a></td>
-            <td><a href="https://www.sfu.ca/~zhenman/">Simon Fraser University</a></td>
-            <td>Vitis U280 XDMA</td>
-            <td>TAPA HLS</td>
-            <td>Accelerator for ORC Decoder.</td>
-        </tr>
-        <tr>
-            <td><a href="benchmarks/tapa_flow/autosa_cnn">Convolutional neural network</a></td>
-            <td><a href="https://dl.acm.org/doi/10.1145/3431920.3439292">Wang <i>et al.</i><br/>(FPGA '21)</a></td>
-            <td>Vitis U250 XDMA</td>
-            <td>TAPA HLS</td>
-            <td>Systolic array accelerator for a convolutional neural network layer.</td>
-        </tr>
-    </tbody>
-</table>
-
 
 How to Get Help
 ---------------

diff --git a/benchmarks/for_dev/bandwidth4/Makefile b/benchmarks/for_dev/bandwidth4/Makefile
@@ -3,9 +3,9 @@
 
 ROOT_DIR         := $(shell git rev-parse --show-toplevel)
 KERNEL_NAME      := bandwidth4
-RS_SCRIPT        := $(CURDIR)/run.py
+RS_SCRIPT        := $(CURDIR)/run_vck5000.py
 SRC_DIR		     := $(CURDIR)/design
-AB_CONFIG        := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/ab_config.json
+AB_CONFIG        := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/floorplan_config.json
 IMPL_CONFIG      := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/impl_config.json
 LINK_CONFIG      := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/link_config.ini
 FIX_NOC_TCL      := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/fix_noc.tcl

diff --git a/...sign/config/run_vck5000.py/ab_config.json → ...nfig/run_vck5000.py/floorplan_config.json b/...sign/config/run_vck5000.py/ab_config.json → ...nfig/run_vck5000.py/floorplan_config.json
diff --git a/benchmarks/for_dev/bandwidth4/design/run_tapa.sh b/benchmarks/for_dev/bandwidth4/design/run_tapa.sh
@@ -0,0 +1,9 @@
+WORK_DIR=work.out
+
+tapa compile \
+  --top bandwidth4 \
+  --part-num xcu55c-fsvh2892-2L-e \
+  --clock-period 3.33 \
+  -o ${WORK_DIR}/bandwidth4.xo \
+  -f src/bandwidth4.cpp \
+  2>&1 | tee tapa.log
diff --git a/benchmarks/tapa_flow/bandwidth23/README.md b/benchmarks/tapa_flow/bandwidth23/README.md
@@ -90,7 +90,7 @@ The RapidStream flow for TAPA requires the following key inputs:
 - **tapa-xo-path**: The path to the tapa-generated `xo` file (bandwidth23.xo).
 - **device-config**: The virtual device (`device.json`) generated in previous step 2 by calling rapidstream APIs based on platform.
 - **floorplan-config**: The configure file ([ab_config.json](design/config/run_vck5000.py/ab_config.json)) to guide integrated Autobridge to floorplan the design.
-- **implementation-config**: The configure file ([impl_config.json](design/config/run_vck5000.py/impl_config.json)) to guide Vitis to implement the design (e.g., kernek clock, vitis_platform and etc.).
+- **implementation-config**: The configure file ([impl_config.json](design/config/run_vck5000.py/impl_config.json)) to guide Vitis to implement the design (e.g., kernel clock, vitis_platform and etc.).
 - **connectivity-ini**: The link configure file ([link_config.ini](design/config/run_vck5000.py/link_config.ini)) to specify how the kernel interfaces are connected the memory controller. This is
 the same for vitis link configure file.
 

diff --git a/benchmarks/tapa_flow/bandwidth52/README.md b/benchmarks/tapa_flow/bandwidth52/README.md
@@ -76,7 +76,7 @@ The RapidStream flow for TAPA requires the following key inputs:
 - **tapa-xo-path**: The path to the tapa-generated `xo` file (bandwidth52.xo).
 - **device-config**: The virtual device (`device.json`) generated in previous step 2 by calling rapidstream APIs based on platform.
 - **floorplan-config**: The configure file ([ab_config.json](design/config/run_vhk158.py/ab_config.json)) to guide integrated Autobridge to floorplan the design.
-- **implementation-config**: The configure file ([impl_config.json](design/config/run_vhk158.py/impl_config.json)) to guide Vitis to implement the design (e.g., kernek clock, vitis_platform and etc.).
+- **implementation-config**: The configure file ([impl_config.json](design/config/run_vhk158.py/impl_config.json)) to guide Vitis to implement the design (e.g., kernel clock, vitis_platform and etc.).
 - **connectivity-ini**: The link configure file ([link_config.ini](design/config/run_vhk158.py/link_config.ini)) to specify how the kernel interfaces are connected the memory controller. This is
 the same for vitis link configure file.
 

diff --git a/benchmarks/tapa_flow/bandwidth52/design/run_tapa.sh b/benchmarks/tapa_flow/bandwidth52/design/run_tapa.sh
@@ -1,9 +1,9 @@
 WORK_DIR=work.out
 
 tapa compile \
-  --top data_decoding \
+  --top bandwidth52 \
   --part-num xcu55c-fsvh2892-2L-e \
   --clock-period 3.33 \
-  -o ${WORK_DIR}/data_decoding.xo \
-  -f src/data_decoder.cpp \
+  -o ${WORK_DIR}/bandwidth52.xo \
+  -f src/bandwidth52.cpp \
   2>&1 | tee tapa.log
diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/Makefile b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/Makefile
@@ -4,7 +4,7 @@
 ROOT_DIR         := $(shell git rev-parse --show-toplevel)
 KERNEL_NAME      := workload
 RS_SCRIPT        := $(CURDIR)/run.py
-AB_CONFIG        := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/ab_config.json
+AB_CONFIG        := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/floorplan_config.json
 IMPL_CONFIG      := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/impl_config.json
 LINK_CONFIG      := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/link_config.ini
 PLATFORM         := xilinx_u55c_gen3x16_xdma_3_202210_1
@@ -32,7 +32,6 @@ $(RS_TARGET):$(TAPA_XO) $(DEVICE_CONFIG)
     --tapa-xo-path $< \
     --device-config $(DEVICE_CONFIG) \
     --floorplan-config $(AB_CONFIG) \
-	--single-reg \
     --run-impl \
     --implementation-config $(IMPL_CONFIG) \
     --connectivity-ini $(LINK_CONFIG)

diff --git a/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/README.md b/benchmarks/tapa_flow/bloomFilter/b3_8_5_8/README.md
@@ -12,7 +12,7 @@ The contributor(s) of this file has/have agreed to the RapidStream Contributor L
 
 In this recipe, we demonstrate how to use RapidStream to optimize TAPA projects. The basic steps include:
 
-- Compile the HLS C++ code into a Vitis-compatible .xo file using TAPA.
+- Compile the TAPA C++ code into a Vitis-compatible .xo file using TAPA.
 - Optimize the .xo file with RapidStream to obtain an optimized .xo file.
 - Use Vitis to compile the optimized .xo file into an .xclbin file for FPGA deployment.
 
@@ -41,10 +41,10 @@ tapa compile \
 The RapidStream flow conducts design space exploration and generates solutions  by taking all TAPA-generated `.xo` file as the input.
 The RapidStream flow for TAPA requires the following key inputs:
 
-- **tapa-xo-path**: The path to the tapa-generated `xo` file (bandwidth52.xo).
+- **tapa-xo-path**: The path to the tapa-generated `xo` file (multistream_MurmurHash3.xo).
 - **device-config**: The virtual device (`device.json`) generated in previous step 2 by calling rapidstream APIs based on platform.
-- **floorplan-config**: The configure file ([ab_config.json](design/config/run.py/ab_config.json)) to guide integrated Autobridge to floorplan the design.
-- **implementation-config**: The configure file ([impl_config.json](design/config/run.py/impl_config.json)) to guide Vitis to implement the design (e.g., kernek clock, vitis_platform and etc.).
+- **floorplan-config**: The configure file ([floorplan_config.json](design/config/run.py/floorplan_config.json)) to guide integrated Autobridge to floorplan the design.
+- **implementation-config**: The configure file ([impl_config.json](design/config/run.py/impl_config.json)) to guide Vitis to implement the design (e.g., kernel clock, vitis_platform and etc.).
 - **connectivity-ini**: The link configure file ([link_config.ini](design/config/run.py/link_config.ini)) to specify how the kernel interfaces are connected the memory controller. This is
 the same for vitis link configure file.
 
@@ -55,7 +55,7 @@ You can run the command below or execute `make all` supported by our [Makefile](
 rapidstream-tapaopt --work-dir build/run.py \
                     --tapa-xo-path ../../design/generated/multistream_MurmurHash3.xo \
                     --device-config build/run.py/device.json \
-                    --floorplan-config design/config/run.py/ab_config.json \
+                    --floorplan-config design/config/run.py/floorplan_config.json \
                     --implementation-config design/config/run.py/impl_config.json \
                     --connectivity-ini design/config/run.py/link_config.ini
 ```

diff --git a/...8_5_8/design/config/run.py/ab_config.json → ...esign/config/run.py/floorplan_config.json b/...8_5_8/design/config/run.py/ab_config.json → ...esign/config/run.py/floorplan_config.json
diff --git a/benchmarks/tapa_flow/bloomFilter/b5_8_5_8/Makefile b/benchmarks/tapa_flow/bloomFilter/b5_8_5_8/Makefile
@@ -4,7 +4,7 @@
 ROOT_DIR         := $(shell git rev-parse --show-toplevel)
 KERNEL_NAME      := workload
 RS_SCRIPT        := $(CURDIR)/run.py
-AB_CONFIG        := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/ab_config.json
+AB_CONFIG        := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/floorplan_config.json
 IMPL_CONFIG      := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/impl_config.json
 LINK_CONFIG      := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/link_config.ini
 PLATFORM         := xilinx_u55c_gen3x16_xdma_3_202210_1
@@ -24,7 +24,6 @@ DEVICE_GEN       := $(CURDIR)/gen_device.py
 
 all: $(RS_TARGET)
 	cd $(RSPATH) && $(RSPYTHON)	$(SLACK_GETTER) -d $(TEMP_DIR) -i $(TIMING_RPT) -o $(BUILD_LOG)  -c clk_kernel_00_unbuffered_net -p 3.333
-	@echo $(SUCCESS)
 
 $(RS_TARGET):$(TAPA_XO) $(DEVICE_CONFIG)
 	mkdir -p $(TEMP_DIR)
@@ -33,7 +32,6 @@ $(RS_TARGET):$(TAPA_XO) $(DEVICE_CONFIG)
     --tapa-xo-path $< \
     --device-config $(DEVICE_CONFIG) \
     --floorplan-config $(AB_CONFIG) \
-	--single-reg \
     --run-impl \
     --implementation-config $(IMPL_CONFIG) \
     --connectivity-ini $(LINK_CONFIG)