Chisel tips&tricks

DontTouch

To prevent the FIRRTL compiler to optimize your structures away wrap them in dontTouch()'s

Wrap-around inc/dec/add/sub

object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } }

pretty print chisel wires before elaboration

    val desc = d match {
      case aggregate: Aggregate => aggregate match {
        case vec: Vec[_] => {
          val children = vec.map((d) => s"${indent * (depth + 1)}${prettyPrintIO(d, depth + 1)},\n"
          ).reduce(_+_)
          s"Vec(\n$children${indent * depth})"
        }
        case record: Record => record match {
          case bundle: Bundle => {
            val className = bundle.getClass.getName
            val name = if (className.contains("$")) bundle.className else className
            val children = bundle.elements.map {
              case (st, d) => s"${indent * (depth + 1)}$st = ${prettyPrintIO(d, depth + 1)}\n"
            }.reduce(_+_)
            s"$name{\n$children${indent * depth}}"
          }
          case _ => record.className
        }
      }
      case element: Element => {
        val widthInfo = s"(${if (element.widthKnown) element.getWidth + ".W" else ""})"
        element match {
          case bool: Bool => "Bool()"
          case uint: UInt => s"UInt($widthInfo)"
          case sint: SInt => s"SInt($widthInfo)"
          case _ => s"${element.getClass.getName}(${if (element.widthKnown) element.getWidth else "?"})"
        }
      }
      case _ => "Data??"
    }
    d.dir match {
      case Chisel.INPUT => s"Input($desc)"
      case Chisel.NODIR => s"$desc"
      case Chisel.OUTPUT => s"Output($desc)"
    }
  }

  println(prettyPrintIO(io))```

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