forked from chipsalliance/rocket-chip
-
Notifications
You must be signed in to change notification settings - Fork 1
TLB
David Metz edited this page Dec 9, 2019
·
8 revisions
-
performance
- does tlb flush on context switch? - selective flushing
- "tag" can't be in cam - too expensive!
- get around huge cam by using phased lookup => shift tlb lookup to s0, use OneHot2UInt + sequential mem for tlc
- does rocket have ASIDs?? - yes
- asid used nowhere in tlb??
- how to make sure entries are not accidentally invalidate by bp? performance only...
-
make sure superpage invalidation is correct (level+comparison) => fragmented superpage??
-
make sure tlb actualy works - not sure about different tags for one entry... - seems correct - because sectored hit is checked
-
thrashing behavior when crossing page boundry in physical mode => need ability to represent more than one physical page in tlb
-
sectored tlb is opposite of what we want! - fuses pages together!
-
debugging infrastructure is big problem - not deterministic - get different execution flows - hard to compare
-
no visibility outside of module scoe (debugging gets harder)
-
make sure replaced/flushed tlb entries don't get lines validated => set invalidated status when tlb is changed while cache is refilling? solved:
-
vaddr = 39 bits => sv39 for 64bit
-
has connection to ptw
-
how to handle superpages?? - no l2 tlb
-
what exactly are superpages?? can they be directly translated?? - higher level pages that can also be leafs
-
ignore superpages => store fractions of them
-
fraction special page
-
what does special entry do?? some kind of memory protection thing if pmp works on sub page granularity
-
what to do when vm is disabled?? flush on change and "translate" physical?
TLB.io = Bundle{
req = chisel3.util.DecoupledIO{
ready = Output(Bool())
valid = Input(Bool())
bits = freechips.rocketchip.rocket.TLBReq{
vaddr = Input(UInt((40.W)))
passthrough = Input(Bool())
size = Input(UInt((2.W)))
cmd = Input(UInt((5.W)))
}
}
resp = freechips.rocketchip.rocket.TLBResp{
miss = Output(Bool())
paddr = Output(UInt((38.W)))
pf = freechips.rocketchip.rocket.TLBExceptions{
ld = Output(Bool())
st = Output(Bool())
inst = Output(Bool())
}
ae = freechips.rocketchip.rocket.TLBExceptions{
ld = Output(Bool())
st = Output(Bool())
inst = Output(Bool())
}
ma = freechips.rocketchip.rocket.TLBExceptions{
ld = Output(Bool())
st = Output(Bool())
inst = Output(Bool())
}
cacheable = Output(Bool())
prefetchable = Output(Bool())
}
sfence = chisel3.util.Valid{
valid = Input(Bool())
bits = freechips.rocketchip.rocket.SFenceReq{
rs1 = Input(Bool())
rs2 = Input(Bool())
addr = Input(UInt((39.W)))
asid = Input(UInt((1.W)))
}
}
ptw = freechips.rocketchip.rocket.TLBPTWIO{
req = chisel3.util.DecoupledIO{
ready = Input(Bool())
valid = Output(Bool())
bits = chisel3.util.Valid{
valid = Output(Bool())
bits = freechips.rocketchip.rocket.PTWReq{
addr = Output(UInt((27.W)))
}
}
}
resp = chisel3.util.Valid{
valid = Input(Bool())
bits = freechips.rocketchip.rocket.PTWResp{
ae = Input(Bool())
pte = freechips.rocketchip.rocket.PTE{
ppn = Input(UInt((54.W)))
reserved_for_software = Input(UInt((2.W)))
d = Input(Bool())
a = Input(Bool())
g = Input(Bool())
u = Input(Bool())
x = Input(Bool())
w = Input(Bool())
r = Input(Bool())
v = Input(Bool())
}
level = Input(UInt((2.W)))
fragmented_superpage = Input(Bool())
homogeneous = Input(Bool())
}
}
ptbr = freechips.rocketchip.rocket.PTBR{
mode = Input(UInt((4.W)))
asid = Input(UInt((16.W)))
ppn = Input(UInt((44.W)))
}
status = freechips.rocketchip.rocket.MStatus{
debug = Input(Bool())
isa = Input(UInt((32.W)))
dprv = Input(UInt((2.W)))
prv = Input(UInt((2.W)))
sd = Input(Bool())
zero2 = Input(UInt((27.W)))
sxl = Input(UInt((2.W)))
uxl = Input(UInt((2.W)))
sd_rv32 = Input(Bool())
zero1 = Input(UInt((8.W)))
tsr = Input(Bool())
tw = Input(Bool())
tvm = Input(Bool())
mxr = Input(Bool())
sum = Input(Bool())
mprv = Input(Bool())
xs = Input(UInt((2.W)))
fs = Input(UInt((2.W)))
mpp = Input(UInt((2.W)))
hpp = Input(UInt((2.W)))
spp = Input(UInt((1.W)))
mpie = Input(Bool())
hpie = Input(Bool())
spie = Input(Bool())
upie = Input(Bool())
mie = Input(Bool())
hie = Input(Bool())
sie = Input(Bool())
uie = Input(Bool())
}
pmp = Vec(
freechips.rocketchip.rocket.PMP{
cfg = freechips.rocketchip.rocket.PMPConfig{
l = Input(Bool())
res = Input(UInt((2.W)))
a = Input(UInt((2.W)))
x = Input(Bool())
w = Input(Bool())
r = Input(Bool())
}
addr = Input(UInt((36.W)))
mask = Input(UInt((38.W)))
},
freechips.rocketchip.rocket.PMP{
cfg = freechips.rocketchip.rocket.PMPConfig{
l = Input(Bool())
res = Input(UInt((2.W)))
a = Input(UInt((2.W)))
x = Input(Bool())
w = Input(Bool())
r = Input(Bool())
}
addr = Input(UInt((36.W)))
mask = Input(UInt((38.W)))
},
freechips.rocketchip.rocket.PMP{
cfg = freechips.rocketchip.rocket.PMPConfig{
l = Input(Bool())
res = Input(UInt((2.W)))
a = Input(UInt((2.W)))
x = Input(Bool())
w = Input(Bool())
r = Input(Bool())
}
addr = Input(UInt((36.W)))
mask = Input(UInt((38.W)))
},
freechips.rocketchip.rocket.PMP{
cfg = freechips.rocketchip.rocket.PMPConfig{
l = Input(Bool())
res = Input(UInt((2.W)))
a = Input(UInt((2.W)))
x = Input(Bool())
w = Input(Bool())
r = Input(Bool())
}
addr = Input(UInt((36.W)))
mask = Input(UInt((38.W)))
},
freechips.rocketchip.rocket.PMP{
cfg = freechips.rocketchip.rocket.PMPConfig{
l = Input(Bool())
res = Input(UInt((2.W)))
a = Input(UInt((2.W)))
x = Input(Bool())
w = Input(Bool())
r = Input(Bool())
}
addr = Input(UInt((36.W)))
mask = Input(UInt((38.W)))
},
freechips.rocketchip.rocket.PMP{
cfg = freechips.rocketchip.rocket.PMPConfig{
l = Input(Bool())
res = Input(UInt((2.W)))
a = Input(UInt((2.W)))
x = Input(Bool())
w = Input(Bool())
r = Input(Bool())
}
addr = Input(UInt((36.W)))
mask = Input(UInt((38.W)))
},
freechips.rocketchip.rocket.PMP{
cfg = freechips.rocketchip.rocket.PMPConfig{
l = Input(Bool())
res = Input(UInt((2.W)))
a = Input(UInt((2.W)))
x = Input(Bool())
w = Input(Bool())
r = Input(Bool())
}
addr = Input(UInt((36.W)))
mask = Input(UInt((38.W)))
},
freechips.rocketchip.rocket.PMP{
cfg = freechips.rocketchip.rocket.PMPConfig{
l = Input(Bool())
res = Input(UInt((2.W)))
a = Input(UInt((2.W)))
x = Input(Bool())
w = Input(Bool())
r = Input(Bool())
}
addr = Input(UInt((36.W)))
mask = Input(UInt((38.W)))
},
)
customCSRs = freechips.rocketchip.rocket.RocketCustomCSRs{
csrs = Vec(
freechips.rocketchip.tile.CustomCSRIO{
wen = Input(Bool())
wdata = Input(UInt((64.W)))
value = Input(UInt((64.W)))
},
freechips.rocketchip.tile.CustomCSRIO{
wen = Input(Bool())
wdata = Input(UInt((64.W)))
value = Input(UInt((64.W)))
},
freechips.rocketchip.tile.CustomCSRIO{
wen = Input(Bool())
wdata = Input(UInt((64.W)))
value = Input(UInt((64.W)))
},
freechips.rocketchip.tile.CustomCSRIO{
wen = Input(Bool())
wdata = Input(UInt((64.W)))
value = Input(UInt((64.W)))
},
)
}
}
kill = Input(Bool())
}