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Frontend
David Metz edited this page Nov 1, 2019
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1 revision
Frontend.io = freechips.rocketchip.rocket.FrontendBundle{
hartid = Input(UInt((1.W)))
reset_vector = Input(UInt((38.W)))
cpu = freechips.rocketchip.rocket.FrontendIO{
might_request = Input(Bool())
req = chisel3.util.Valid{
valid = Input(Bool())
bits = freechips.rocketchip.rocket.FrontendReq{
pc = Input(UInt((40.W)))
speculative = Input(Bool())
}
}
sfence = chisel3.util.Valid{
valid = Input(Bool())
bits = freechips.rocketchip.rocket.SFenceReq{
rs1 = Input(Bool())
rs2 = Input(Bool())
addr = Input(UInt((39.W)))
asid = Input(UInt((1.W)))
}
}
resp = chisel3.util.DecoupledIO{
ready = Input(Bool())
valid = Output(Bool())
bits = freechips.rocketchip.rocket.FrontendResp{
btb = freechips.rocketchip.rocket.BTBResp{
cfiType = Output(UInt((2.W)))
taken = Output(Bool())
mask = Output(UInt((2.W)))
bridx = Output(UInt((1.W)))
target = Output(UInt((39.W)))
entry = Output(UInt((5.W)))
bht = freechips.rocketchip.rocket.BHTResp{
history = Output(UInt((8.W)))
value = Output(UInt((1.W)))
}
}
pc = Output(UInt((40.W)))
data = Output(UInt((32.W)))
mask = Output(UInt((2.W)))
xcpt = freechips.rocketchip.rocket.FrontendExceptions{
pf = Bundle{
inst = Output(Bool())
}
ae = Bundle{
inst = Output(Bool())
}
}
replay = Output(Bool())
}
}
btb_update = chisel3.util.Valid{
valid = Input(Bool())
bits = freechips.rocketchip.rocket.BTBUpdate{
prediction = freechips.rocketchip.rocket.BTBResp{
cfiType = Input(UInt((2.W)))
taken = Input(Bool())
mask = Input(UInt((2.W)))
bridx = Input(UInt((1.W)))
target = Input(UInt((39.W)))
entry = Input(UInt((5.W)))
bht = freechips.rocketchip.rocket.BHTResp{
history = Input(UInt((8.W)))
value = Input(UInt((1.W)))
}
}
pc = Input(UInt((39.W)))
target = Input(UInt((39.W)))
taken = Input(Bool())
isValid = Input(Bool())
br_pc = Input(UInt((39.W)))
cfiType = Input(UInt((2.W)))
}
}
bht_update = chisel3.util.Valid{
valid = Input(Bool())
bits = freechips.rocketchip.rocket.BHTUpdate{
prediction = freechips.rocketchip.rocket.BHTResp{
history = Input(UInt((8.W)))
value = Input(UInt((1.W)))
}
pc = Input(UInt((39.W)))
branch = Input(Bool())
taken = Input(Bool())
mispredict = Input(Bool())
}
}
ras_update = chisel3.util.Valid{
valid = Input(Bool())
bits = freechips.rocketchip.rocket.RASUpdate{
cfiType = Input(UInt((2.W)))
returnAddr = Input(UInt((39.W)))
}
}
flush_icache = Input(Bool())
npc = Output(UInt((40.W)))
perf = freechips.rocketchip.rocket.FrontendPerfEvents{
acquire = Output(Bool())
tlbMiss = Output(Bool())
}
}
ptw = freechips.rocketchip.rocket.TLBPTWIO{
req = chisel3.util.DecoupledIO{
ready = Input(Bool())
valid = Output(Bool())
bits = chisel3.util.Valid{
valid = Output(Bool())
bits = freechips.rocketchip.rocket.PTWReq{
addr = Output(UInt((27.W)))
}
}
}
resp = chisel3.util.Valid{
valid = Input(Bool())
bits = freechips.rocketchip.rocket.PTWResp{
ae = Input(Bool())
pte = freechips.rocketchip.rocket.PTE{
ppn = Input(UInt((54.W)))
reserved_for_software = Input(UInt((2.W)))
d = Input(Bool())
a = Input(Bool())
g = Input(Bool())
u = Input(Bool())
x = Input(Bool())
w = Input(Bool())
r = Input(Bool())
v = Input(Bool())
}
level = Input(UInt((2.W)))
fragmented_superpage = Input(Bool())
homogeneous = Input(Bool())
}
}
ptbr = freechips.rocketchip.rocket.PTBR{
mode = Input(UInt((4.W)))
asid = Input(UInt((16.W)))
ppn = Input(UInt((44.W)))
}
status = freechips.rocketchip.rocket.MStatus{
debug = Input(Bool())
isa = Input(UInt((32.W)))
dprv = Input(UInt((2.W)))
prv = Input(UInt((2.W)))
sd = Input(Bool())
zero2 = Input(UInt((27.W)))
sxl = Input(UInt((2.W)))
uxl = Input(UInt((2.W)))
sd_rv32 = Input(Bool())
zero1 = Input(UInt((8.W)))
tsr = Input(Bool())
tw = Input(Bool())
tvm = Input(Bool())
mxr = Input(Bool())
sum = Input(Bool())
mprv = Input(Bool())
xs = Input(UInt((2.W)))
fs = Input(UInt((2.W)))
mpp = Input(UInt((2.W)))
hpp = Input(UInt((2.W)))
spp = Input(UInt((1.W)))
mpie = Input(Bool())
hpie = Input(Bool())
spie = Input(Bool())
upie = Input(Bool())
mie = Input(Bool())
hie = Input(Bool())
sie = Input(Bool())
uie = Input(Bool())
}
pmp = Vec(
freechips.rocketchip.rocket.PMP{
cfg = freechips.rocketchip.rocket.PMPConfig{
l = Input(Bool())
res = Input(UInt((2.W)))
a = Input(UInt((2.W)))
x = Input(Bool())
w = Input(Bool())
r = Input(Bool())
}
addr = Input(UInt((36.W)))
mask = Input(UInt((38.W)))
},
freechips.rocketchip.rocket.PMP{
cfg = freechips.rocketchip.rocket.PMPConfig{
l = Input(Bool())
res = Input(UInt((2.W)))
a = Input(UInt((2.W)))
x = Input(Bool())
w = Input(Bool())
r = Input(Bool())
}
addr = Input(UInt((36.W)))
mask = Input(UInt((38.W)))
},
freechips.rocketchip.rocket.PMP{
cfg = freechips.rocketchip.rocket.PMPConfig{
l = Input(Bool())
res = Input(UInt((2.W)))
a = Input(UInt((2.W)))
x = Input(Bool())
w = Input(Bool())
r = Input(Bool())
}
addr = Input(UInt((36.W)))
mask = Input(UInt((38.W)))
},
freechips.rocketchip.rocket.PMP{
cfg = freechips.rocketchip.rocket.PMPConfig{
l = Input(Bool())
res = Input(UInt((2.W)))
a = Input(UInt((2.W)))
x = Input(Bool())
w = Input(Bool())
r = Input(Bool())
}
addr = Input(UInt((36.W)))
mask = Input(UInt((38.W)))
},
freechips.rocketchip.rocket.PMP{
cfg = freechips.rocketchip.rocket.PMPConfig{
l = Input(Bool())
res = Input(UInt((2.W)))
a = Input(UInt((2.W)))
x = Input(Bool())
w = Input(Bool())
r = Input(Bool())
}
addr = Input(UInt((36.W)))
mask = Input(UInt((38.W)))
},
freechips.rocketchip.rocket.PMP{
cfg = freechips.rocketchip.rocket.PMPConfig{
l = Input(Bool())
res = Input(UInt((2.W)))
a = Input(UInt((2.W)))
x = Input(Bool())
w = Input(Bool())
r = Input(Bool())
}
addr = Input(UInt((36.W)))
mask = Input(UInt((38.W)))
},
freechips.rocketchip.rocket.PMP{
cfg = freechips.rocketchip.rocket.PMPConfig{
l = Input(Bool())
res = Input(UInt((2.W)))
a = Input(UInt((2.W)))
x = Input(Bool())
w = Input(Bool())
r = Input(Bool())
}
addr = Input(UInt((36.W)))
mask = Input(UInt((38.W)))
},
freechips.rocketchip.rocket.PMP{
cfg = freechips.rocketchip.rocket.PMPConfig{
l = Input(Bool())
res = Input(UInt((2.W)))
a = Input(UInt((2.W)))
x = Input(Bool())
w = Input(Bool())
r = Input(Bool())
}
addr = Input(UInt((36.W)))
mask = Input(UInt((38.W)))
},
)
customCSRs = freechips.rocketchip.rocket.RocketCustomCSRs{
csrs = Vec(
freechips.rocketchip.tile.CustomCSRIO{
wen = Input(Bool())
wdata = Input(UInt((64.W)))
value = Input(UInt((64.W)))
},
freechips.rocketchip.tile.CustomCSRIO{
wen = Input(Bool())
wdata = Input(UInt((64.W)))
value = Input(UInt((64.W)))
},
freechips.rocketchip.tile.CustomCSRIO{
wen = Input(Bool())
wdata = Input(UInt((64.W)))
value = Input(UInt((64.W)))
},
freechips.rocketchip.tile.CustomCSRIO{
wen = Input(Bool())
wdata = Input(UInt((64.W)))
value = Input(UInt((64.W)))
},
)
}
}
errors = freechips.rocketchip.rocket.ICacheErrors{
}
}