TestHarness

dut

• ports of dut

dut.clock = Input(chisel3.core.Clock(1))
dut.reset = Input(Bool())
dut.auto = freechips.rocketchip.diplomacy.AutoBundle{
}
dut.debug = freechips.rocketchip.devices.debug.DebugIO{
  clockeddmi = freechips.rocketchip.devices.debug.ClockedDMIIO{
    dmi = freechips.rocketchip.devices.debug.DMIIO{
      req = chisel3.util.DecoupledIO{
        ready = Output(Bool())
        valid = Input(Bool())
        bits = freechips.rocketchip.devices.debug.DMIReq{
          addr = Input(UInt((7.W)))
          data = Input(UInt((32.W)))
          op = Input(UInt((2.W)))
        }
      }
      resp = chisel3.util.DecoupledIO{
        ready = Input(Bool())
        valid = Output(Bool())
        bits = freechips.rocketchip.devices.debug.DMIResp{
          data = Output(UInt((32.W)))
          resp = Output(UInt((2.W)))
        }
      }
    }
    dmiClock = Input(chisel3.core.Clock(1))
    dmiReset = Input(Bool())
  }
  ndreset = Output(Bool())
  dmactive = Output(Bool())
}
dut.interrupts = Input(UInt((2.W)))
dut.mem_axi4 = freechips.rocketchip.util.HeterogeneousBag{
  0 = freechips.rocketchip.amba.axi4.AXI4Bundle{
    aw = chisel3.util.IrrevocableIO{
      ready = Input(Bool())
      valid = Output(Bool())
      bits = freechips.rocketchip.amba.axi4.AXI4BundleAW{
        id = Output(UInt((4.W)))
        addr = Output(UInt((32.W)))
        len = Output(UInt((8.W)))
        size = Output(UInt((3.W)))
        burst = Output(UInt((2.W)))
        lock = Output(UInt((1.W)))
        cache = Output(UInt((4.W)))
        prot = Output(UInt((3.W)))
        qos = Output(UInt((4.W)))
      }
    }
    w = chisel3.util.IrrevocableIO{
      ready = Input(Bool())
      valid = Output(Bool())
      bits = freechips.rocketchip.amba.axi4.AXI4BundleW{
        data = Output(UInt((64.W)))
        strb = Output(UInt((8.W)))
        last = Output(Bool())
      }
    }
    b = chisel3.util.IrrevocableIO{
      ready = Output(Bool())
      valid = Input(Bool())
      bits = freechips.rocketchip.amba.axi4.AXI4BundleB{
        id = Input(UInt((4.W)))
        resp = Input(UInt((2.W)))
      }
    }
    ar = chisel3.util.IrrevocableIO{
      ready = Input(Bool())
      valid = Output(Bool())
      bits = freechips.rocketchip.amba.axi4.AXI4BundleAR{
        id = Output(UInt((4.W)))
        addr = Output(UInt((32.W)))
        len = Output(UInt((8.W)))
        size = Output(UInt((3.W)))
        burst = Output(UInt((2.W)))
        lock = Output(UInt((1.W)))
        cache = Output(UInt((4.W)))
        prot = Output(UInt((3.W)))
        qos = Output(UInt((4.W)))
      }
    }
    r = chisel3.util.IrrevocableIO{
      ready = Output(Bool())
      valid = Input(Bool())
      bits = freechips.rocketchip.amba.axi4.AXI4BundleR{
        id = Input(UInt((4.W)))
        data = Input(UInt((64.W)))
        resp = Input(UInt((2.W)))
        last = Input(Bool())
      }
    }
  }
}
dut.mmio_axi4 = freechips.rocketchip.util.HeterogeneousBag{
  0 = freechips.rocketchip.amba.axi4.AXI4Bundle{
    aw = chisel3.util.IrrevocableIO{
      ready = Input(Bool())
      valid = Output(Bool())
      bits = freechips.rocketchip.amba.axi4.AXI4BundleAW{
        id = Output(UInt((4.W)))
        addr = Output(UInt((31.W)))
        len = Output(UInt((8.W)))
        size = Output(UInt((3.W)))
        burst = Output(UInt((2.W)))
        lock = Output(UInt((1.W)))
        cache = Output(UInt((4.W)))
        prot = Output(UInt((3.W)))
        qos = Output(UInt((4.W)))
      }
    }
    w = chisel3.util.IrrevocableIO{
      ready = Input(Bool())
      valid = Output(Bool())
      bits = freechips.rocketchip.amba.axi4.AXI4BundleW{
        data = Output(UInt((64.W)))
        strb = Output(UInt((8.W)))
        last = Output(Bool())
      }
    }
    b = chisel3.util.IrrevocableIO{
      ready = Output(Bool())
      valid = Input(Bool())
      bits = freechips.rocketchip.amba.axi4.AXI4BundleB{
        id = Input(UInt((4.W)))
        resp = Input(UInt((2.W)))
      }
    }
    ar = chisel3.util.IrrevocableIO{
      ready = Input(Bool())
      valid = Output(Bool())
      bits = freechips.rocketchip.amba.axi4.AXI4BundleAR{
        id = Output(UInt((4.W)))
        addr = Output(UInt((31.W)))
        len = Output(UInt((8.W)))
        size = Output(UInt((3.W)))
        burst = Output(UInt((2.W)))
        lock = Output(UInt((1.W)))
        cache = Output(UInt((4.W)))
        prot = Output(UInt((3.W)))
        qos = Output(UInt((4.W)))
      }
    }
    r = chisel3.util.IrrevocableIO{
      ready = Output(Bool())
      valid = Input(Bool())
      bits = freechips.rocketchip.amba.axi4.AXI4BundleR{
        id = Input(UInt((4.W)))
        data = Input(UInt((64.W)))
        resp = Input(UInt((2.W)))
        last = Input(Bool())
      }
    }
  }
}
dut.l2_frontend_bus_axi4 = freechips.rocketchip.util.HeterogeneousBag{
  0 = freechips.rocketchip.amba.axi4.AXI4Bundle{
    aw = chisel3.util.IrrevocableIO{
      ready = Output(Bool())
      valid = Input(Bool())
      bits = freechips.rocketchip.amba.axi4.AXI4BundleAW{
        id = Input(UInt((8.W)))
        addr = Input(UInt((32.W)))
        len = Input(UInt((8.W)))
        size = Input(UInt((3.W)))
        burst = Input(UInt((2.W)))
        lock = Input(UInt((1.W)))
        cache = Input(UInt((4.W)))
        prot = Input(UInt((3.W)))
        qos = Input(UInt((4.W)))
      }
    }
    w = chisel3.util.IrrevocableIO{
      ready = Output(Bool())
      valid = Input(Bool())
      bits = freechips.rocketchip.amba.axi4.AXI4BundleW{
        data = Input(UInt((64.W)))
        strb = Input(UInt((8.W)))
        last = Input(Bool())
      }
    }
    b = chisel3.util.IrrevocableIO{
      ready = Input(Bool())
      valid = Output(Bool())
      bits = freechips.rocketchip.amba.axi4.AXI4BundleB{
        id = Output(UInt((8.W)))
        resp = Output(UInt((2.W)))
      }
    }
    ar = chisel3.util.IrrevocableIO{
      ready = Output(Bool())
      valid = Input(Bool())
      bits = freechips.rocketchip.amba.axi4.AXI4BundleAR{
        id = Input(UInt((8.W)))
        addr = Input(UInt((32.W)))
        len = Input(UInt((8.W)))
        size = Input(UInt((3.W)))
        burst = Input(UInt((2.W)))
        lock = Input(UInt((1.W)))
        cache = Input(UInt((4.W)))
        prot = Input(UInt((3.W)))
        qos = Input(UInt((4.W)))
      }
    }
    r = chisel3.util.IrrevocableIO{
      ready = Input(Bool())
      valid = Output(Bool())
      bits = freechips.rocketchip.amba.axi4.AXI4BundleR{
        id = Output(UInt((8.W)))
        data = Output(UInt((64.W)))
        resp = Output(UInt((2.W)))
        last = Output(Bool())
      }
    }
  }
}