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David Metz edited this page Dec 9, 2019 · 14 revisions

usefull stuff

https://github.com/riscv/riscv-asm-manual/blob/master/riscv-asm.md

setting up Intellij:

  • import sbt (use sbt shell for build and import)
  • in sbt shell in intellij: ++2.12.4
  • set correct sdk version (2.12.4)
  • need to rerun ++2.12.4 at startup - haven't figured out workaround yet

preserve unused signals in simulation

  • wrap in dontTouch

emulator workflow

make debug

  • analysis of steps taken

generate flirtl

  • sbt "runMain freechips.rocketchip.system.Generator /home/david/git/freedom/rocket-chip/emulator/generated-src freechips.rocketchip.system TestHarness freechips.rocketchip.system DefaultConfig"

  • translates roughly into (doesn't really work; expects some kind of builder context - real version in system/Generator)

// values used in Generator
val targetDir = "/home/david/git/freedom/rocket-chip/emulator/generated-src "
val topModuleProject = "freechips.rocketchip.system"
val topModuleClass = "TestHarness"
val configProject = "freechips.rocketchip.system"
val configs = "DefaultConfig"

import freechips.rocketchip.system.TestHarness
import freechips.rocketchip.system.DefaultConfig
val config = new Config(new DefaultConfig)
// implicit is some kind of magic that selects it as default parameter
implicit val params: Parameters = config.toInstance
val module =  new TestHarness()(params)
Driver.elaborate(() => module)

generate verilog

java -Xmx2G -Xss8M -XX:MaxPermSize=256M -cp "/home/david/git/freedom/rocket-chip/firrtl/utils/bin/firrtl.jar":""/home/david/git/freedom/rocket-chip/target/scala-2.12/classes:/home/david/git/freedom/rocket-chip/chisel3/target/scala-2.12/*"" firrtl.Driver -i /home/david/git/freedom/rocket-chip/emulator/generated-src/freechips.rocketchip.system.DefaultConfig.fir -o /home/david/git/freedom/rocket-chip/emulator/generated-src/freechips.rocketchip.system.DefaultConfig.v -X verilog --infer-rw TestHarness --repl-seq-mem -c:TestHarness:-o:/home/david/git/freedom/rocket-chip/emulator/generated-src/freechips.rocketchip.system.DefaultConfig.conf -faf /home/david/git/freedom/rocket-chip/emulator/generated-src/freechips.rocketchip.system.DefaultConfig.anno.json -td /home/david/git/freedom/rocket-chip/emulator/generated-src/freechips.rocketchip.system.DefaultConfig/

generate sram verilog

cd /home/david/git/freedom/rocket-chip/emulator/generated-src && \
/home/david/git/freedom/rocket-chip/scripts/vlsi_mem_gen /home/david/git/freedom/rocket-chip/emulator/generated-src/freechips.rocketchip.system.DefaultConfig.conf > /home/david/git/freedom/rocket-chip/emulator/generated-src/freechips.rocketchip.system.DefaultConfig.behav_srams.v.tmp && \
mv -f /home/david/git/freedom/rocket-chip/emulator/generated-src/freechips.rocketchip.system.DefaultConfig.behav_srams.v.tmp /home/david/git/freedom/rocket-chip/emulator/generated-src/freechips.rocketchip.system.DefaultConfig.behav_srams.v

generate verilator

/home/david/git/freedom/rocket-chip/emulator/verilator/install/bin/verilator --cc --exe --top-module TestHarness +define+PRINTF_COND=\$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) +define+RANDOMIZE_GARBAGE_ASSIGN +define+STOP_COND=\$c\(\"done_reset\"\) --assert --output-split 20000 --output-split-cfuncs 20000 -Wno-STMTDLY --x-assign unique -I/home/david/git/freedom/rocket-chip/src/main/resources/vsrc -O3 -CFLAGS "-O1 -std=c++11 -I/home/david/git/rocket-tools/toolchain/include -DVERILATOR -DTEST_HARNESS=VTestHarness -include /home/david/git/freedom/rocket-chip/src/main/resources/csrc/verilator.h -include /home/david/git/freedom/rocket-chip/emulator/generated-src/freechips.rocketchip.system.DefaultConfig.plusArgs" -Mdir /home/david/git/freedom/rocket-chip/emulator/generated-src-debug/freechips.rocketchip.system.DefaultConfig  --trace \
-o /home/david/git/freedom/rocket-chip/emulator/emulator-freechips.rocketchip.system-DefaultConfig-debug /home/david/git/freedom/rocket-chip/emulator/generated-src/freechips.rocketchip.system.DefaultConfig.v /home/david/git/freedom/rocket-chip/emulator/generated-src/freechips.rocketchip.system.DefaultConfig.behav_srams.v  /home/david/git/freedom/rocket-chip/src/main/resources/csrc/emulator.cc /home/david/git/freedom/rocket-chip/src/main/resources/csrc/SimDTM.cc /home/david/git/freedom/rocket-chip/src/main/resources/csrc/SimJTAG.cc /home/david/git/freedom/rocket-chip/src/main/resources/csrc/remote_bitbang.cc -LDFLAGS " -L/home/david/git/rocket-tools/toolchain/lib -Wl,-rpath,/home/david/git/rocket-tools/toolchain/lib -L/home/david/git/freedom/rocket-chip/emulator -lfesvr -lpthread" \
-CFLAGS "-I/home/david/git/freedom/rocket-chip/emulator/generated-src-debug -include /home/david/git/freedom/rocket-chip/emulator/generated-src-debug/freechips.rocketchip.system.DefaultConfig/VTestHarness.h"
  • build make -j8 VM_PARALLEL_BUILDS=1 -C /home/david/git/freedom/rocket-chip/emulator/generated-src-debug/freechips.rocketchip.system.DefaultConfig -f VTestHarness.mk

verilator deep dive

speedup

  • ~20s to generate fir
  • ~35s to compile fir to v
  • ~5min total => verilator/gcc step dominates

soc

defualt memory map

Generated Address Map
	       0 -     1000 ARWX  debug-controller@0
	    3000 -     4000 ARWX  error-device@3000
	   10000 -    20000  R X  rom@10000                     //tilelink/BootROM.scala  
	 2000000 -  2010000 ARW   clint@2000000
	 c000000 - 10000000 ARW   interrupt-controller@c000000
	60000000 - 80000000  RWX  mmio-port-axi4@60000000
	80000000 - 90000000  RWXC memory@80000000               //subsystem/Ports.scala - CanHaveMasterAXI4MemPort

rocket

  • s1, s2,...sn delayed by n cycles in relation to req

  • register file = rf in RocketCore

  • ICache -> IBuf -> decode

  • how is ICache connected to mem??

  • difference between DCache and NBDcache??

    • DCache when nMSHRs == 0 (for all default CPU configs) => ignore NBDCache

  • hartId = hardware thread id

emulator

cd git/freedom/rocket-chip/emulator/ make debug CONFIG=DefaultNaiveConfig make test CONFIG=DefaultNaiveConfig make -j6 run-asm-tests CONFIG=DefaultNaiveConfig grep -R "TLB" output regex : "C0: (\d)+"

Masterplan:

  • simplyfy icache
  • move tlb from frontend into icache
  • create simplified tlb
    • remove superpages
    • test superpages
    • figure out special_entry
  • unify them into tlc
  • speed up emulator
    • ~5% actual program - rest overhead
    • load simple elf file usinf emulator => fast
      • strip down elf file but keep _start and tohost
        • $RISCV/bin/riscv64-unknown-elf-objcopy --update-section .text.init=empty_file -R .text -R .rodata.str1.8 -R .bss -R .comment -S -K _start -K fromhost -K tohost test.elf test_modified.elf
    • load rest into memory using loadmem
    • fromhost and tohost need right value
      • generate suitable empty elf file
    • SREC http://www.electronicsfaq.com/2011/09/motorola-s-record-file.html $RISCV/bin/riscv64-unknown-elf-objcopy -O srec test.elf test.srec

Report TODO:

Introduction

  • RISC-V
  • Open source hardware
  • energy efficency
  • chisel high level HDL
  • overview

Background

  • RISC-V
    • ICache Memory Model
    • Virtual Memory
    • Memory Protection?
  • TileLink
  • Diplomacy
  • COnfiguration
  • test programs ###TLC

Implementation

Results

  • Runtime

Discussion/Future work

  • run linux and proper benchmarks
  • get FPGA subsystem to work
  • use yosys + freepdk + openram as open source ASIC synthesis toolchain
  • optimze
  • modify TLB to use set accosiative design + change lookup to sequential
  • use micropages + increase associativity (2**n-1)-way - 0 as invalid - disadvantage: must write WP for invalidation
  • evaluate TLC DCache
  • bring back ECC
  • evaluate other optimisations

Conclusion

  • Too many unknowns in performance evaluation

Evaluation:

FPGA:

  • modify rocket config in src/main/scala/ntnu/zynq/Config.scala
  • generate NtnuRocketZynq verilog cd ~/git/freedom make -f Makefile.NtnuRocketZynq verilog
  • generate quartus project & synthesize cd ~/git/parallella-riscv ./scripts/build.fpga.bitstream.sh

Methodology:

create_project tlc_eval /home/david/git/freedom/builds/NtnuRocketZynq/tlc_eval -part xc7z020clg400-1 set_property board_part digilentinc.com:arty-z7-20:part0:1.0 [current_project] add_files {/home/david/git/freedom/builds/NtnuRocketZynq/ntnu.zynq.NtnuRocketZynqConfig.v /home/david/git/freedom/builds/NtnuRocketZynq/verilog_wrapper } set top_module NtnuRocketZynqTop set_property STEPS.WRITE_BITSTREAM.TCL.PRE {/home/david/git/freedom_zybo/freedom/fpga-shells/xilinx/zybo/tcl/no_connect.tcl} [get_runs impl_1]

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